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| S3C880A/F880A 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 3 Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product. S3C880A/F880A 8-Bit CMOS Microcontrollers User's Manual, Revision 3 Publication Number: 23-S3-C880A/F880A-072004 (c) 2004 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics. Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BSI Certificate No. FM24653). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Kiheung-Eup Yongin-City, Kyunggi-Do, Korea C.P.O. Box #37, Suwon 449-900 TEL: (82)-(31)-209-1907 FAX: (82)-(31)-209-1889 Home-Page URL: Http://www.intl.samsungsemi.com Printed in the Republic of Korea Preface The S3C880A/F880A Microcontroller User's Manual is designed for application designers and programmers who are using the S3C880A/F880A microcontroller for application development. It is organized in two main parts: Part I Programming Model Part II Hardware Descriptions Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has six chapters: Chapter 1 Chapter 2 Chapter 3 Product Overview Address Spaces Addressing Modes Chapter 4 Chapter 5 Chapter 6 Control Registers Interrupt Structure SAM8 Instruction Set Chapter 1, "Product Overview," is a high-level introduction to S3C880A/F880A with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types. Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations. Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the S3C8-series CPU. Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs. Chapter 5, "Interrupt Structure," describes the S3C880A/F880A interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II. Chapter 6, "SAM8 Instruction Set," describes the features and conventions of the instruction set used for all S3C8series microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of each instruction are presented in a standard format. Each instruction description includes one or more practical examples of how to use the instruction when writing an application program. A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in Part II. If you are not yet familiar with the S3C8-series microcontroller family and are reading this manual for the first time, we recommend that you first read Chapters 1-3 carefully. Then, briefly look over the detailed information in Chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary. Part II "hardware Descriptions," has detailed information about specific hardware components of the S3C880A/F880A microcontroller. Also included in Part II are electrical, mechanical, MTP, and development tools data. It has 11 chapters: Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Clock Circuits nRESET and Power-Down I/O Ports Basic Timer and Timer 0 Timer A PWM and Capture Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 On-Screen Display (OSD) Analog-to-Digital Converter Electrical Data Mechanical Data S3F880A MTP Development Tools Two order forms are included at the back of this manual to facilitate customer order for S3C880A/F880A microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative. S3C880A/F880A MICROCONTROLLER iii Table of Contents Part I -- Programming Model Chapter 1 Product Overview Overview .............................................................................................................................................1-1 Features .............................................................................................................................................1-2 Block Diagram ....................................................................................................................................1-3 Pin Assignments.................................................................................................................................1-4 Pin Descriptions ..................................................................................................................................1-5 Pin Circuits.........................................................................................................................................1-7 Chapter 2 Address Spaces Overview .............................................................................................................................................2-1 Program Memory (ROM) ......................................................................................................................2-2 Register Architecture ...........................................................................................................................2-3 ROM Code Option (RCOD_OPT)...........................................................................................................2-5 Register Page Pointer (PP) ..........................................................................................................2-6 Effect of Different Instructions For Inter-Page Data Operations .........................................................2-7 Register Set 1.............................................................................................................................2-14 Register Set 2.............................................................................................................................2-14 Prime Register Space..................................................................................................................2-14 Working Registers .......................................................................................................................2-16 Using The Register Pointers .........................................................................................................2-17 Register Addressing ............................................................................................................................2-19 Common Working Register Area (C0H-CFH) .................................................................................2-21 4-Bit Working Register Addressing................................................................................................2-22 8-Bit Working Register Addressing................................................................................................2-24 System and User Stacks .....................................................................................................................2-26 Chapter 3 Addressing Modes Overview .............................................................................................................................................3-1 Register Addressing Mode (R) ......................................................................................................3-2 Indirect Register Addressing Mode (IR)..........................................................................................3-3 Indexed Addressing Mode (X) .......................................................................................................3-7 Direct Address Mode (DA)............................................................................................................3-10 Indirect Address Mode (IA)...........................................................................................................3-12 Relative Address Mode (RA).........................................................................................................3-13 Immediate Mode (IM) ...................................................................................................................3-14 S3C880A/F880A MICROCONTROLLER v Table of Contents Chapter 4 Control Registers (Continued) Overview .............................................................................................................................................4-1 Chapter 5 Interrupt Structure Overview .............................................................................................................................................5-1 Interrupt Types ............................................................................................................................5-1 S3C880A/F880A Interrupt Structure ..............................................................................................5-2 Interrupt Vector Addresses ...........................................................................................................5-4 Enable/Disable Interrupt Instructions (EI, DI) ..................................................................................5-6 System-Level Interrupt Control Registers .......................................................................................5-6 Interrupt Processing Control Points ...............................................................................................5-7 Peripheral Interrupt Control Registers ............................................................................................5-8 System Mode Register (SYM) ......................................................................................................5-9 Interrupt Mask Register (IMR) .......................................................................................................5-10 Interrupt Priority Register (IPR) .....................................................................................................5-11 Interrupt Request Register (IRQ) ...................................................................................................5-12 Interrupt Pending Function Types ..................................................................................................5-13 Interrupt Source Polling Sequence ................................................................................................5-14 Interrupt Service Routines.............................................................................................................5-14 Generating Interrupt Vector Addresses ..........................................................................................5-15 Nesting of Vectored Interrupts.......................................................................................................5-15 Instruction Pointer (IP) .................................................................................................................5-15 Fast Interrupt Processing .............................................................................................................5-16 Chapter 6 SAM8 Instruction Set Overview .............................................................................................................................................6-1 Data Types .................................................................................................................................6-1 Register Addressing ....................................................................................................................6-1 Addressing Modes.......................................................................................................................6-1 Flags Register (FLAGS)...............................................................................................................6-6 Flag Descriptions ........................................................................................................................6-7 Instruction Set Notation................................................................................................................6-8 Condition Codes ..........................................................................................................................6-12 Instruction Descriptions................................................................................................................6-13 vi S3C880A/F880A MICROCONTROLLER Table of Contents (Continued) Part II Hardware Descriptions Chapter 7 Clock Circuit Overview .............................................................................................................................................7-1 System Clock Circuit...................................................................................................................7-1 Clock Status During Power-Down Modes .......................................................................................7-2 System Clock Control Register (CLKCON).....................................................................................7-3 Relation Between L-C Oscillator and CPU Clock ............................................................................7-5 Chapter 8 nRESET and Power-Down System Reset .....................................................................................................................................8-1 Overview .....................................................................................................................................8-1 Hardware Reset Values................................................................................................................8-2 Power-Down Modes .............................................................................................................................8-5 Stop Mode..................................................................................................................................8-5 Idle Mode....................................................................................................................................8-6 Chapter 9 I/O Ports Overview .............................................................................................................................................9-1 Port Data Registers .....................................................................................................................9-2 Port 0.........................................................................................................................................9-2 Port 1.........................................................................................................................................9-4 Port 2.........................................................................................................................................9-5 Port 3.........................................................................................................................................9-6 Chapter 10 Basic Timer and Timer 0 Module Overview..................................................................................................................................10-1 Basic Timer Control Register (BTCON) ..........................................................................................10-2 Basic Timer Function Description..................................................................................................10-3 Timer 0 Control Register (T0CON) .................................................................................................10-6 Timer 0 Function Description ........................................................................................................10-7 S3C880A/F880A MICROCONTROLLER vii Table of Contents Chapter 11 Timer A (Continued) Overview .............................................................................................................................................11-1 Timer Clock Input ........................................................................................................................11-1 Timer A Interrupt Control ..............................................................................................................11-1 Timer A Function Description........................................................................................................11-2 Timer A Control Register (TACON) ................................................................................................11-3 Chapter 12 PWM and Capture PWM/Capture Module..........................................................................................................................12-1 PWM Control Register (PWMCON)...............................................................................................12-2 PWM2-PWM5....................................................................................................................................12-3 PWM2-PWM5 Function Description .............................................................................................12-4 Staggered PWM Outputs .............................................................................................................12-5 PWM0-PWM1....................................................................................................................................12-7 PWM Counter .............................................................................................................................12-7 PWM Data and Extension Registers .............................................................................................12-7 PWM Clock Rate ........................................................................................................................12-7 PWM0 and PWM1 Function Description........................................................................................12-8 Capture Unit................................................................................................................................12-12 Chapter 13 On-Screen Display (OSD) Overview .............................................................................................................................................13-1 Pattern Generation Software.........................................................................................................13-1 Internal OSD Clock......................................................................................................................13-2 OSD Video RAM .........................................................................................................................13-2 OSD Control Register Overview.............................................................................................................13-5 Display Control Register (DSPCON)..............................................................................................13-6 Character Size Control Register (CHACON) ...................................................................................13-8 Fade-In and Fade-Out Control Register (FADECON) .......................................................................13-10 Display Position Control.......................................................................................................................13-14 Row Control Register (ROWCON) .................................................................................................13-15 Column Control Register (CLMCON)..............................................................................................13-15 Character Color Control Register (COLBUF)...................................................................................13-17 Background Color Control.....................................................................................................................13-18 V-SYNC Blank Control Register (VSBCON) ...................................................................................13-20 V-SYNC Blank and Top Margin Timing Diagram .............................................................................13-21 Halftone Signal Control Register (HTCON)......................................................................................13-22 OSD Field Control Register (OSDFLD) ..................................................................................................13-25 OSD Palette Color Control............................................................................................................13-27 OSD Space Color Control Register (OSDCOL) ...............................................................................13-31 OSD Border/Fringe Function.........................................................................................................13-33 OSD Smooth Fucntion.................................................................................................................13-35 viii S3C880A/F880A MICROCONTROLLER Table of Contents Chapter 14 (Concluded) Analog-to-Digital Converter Overview .............................................................................................................................................14-1 Using A/D Pins for Standard Digital Input .......................................................................................14-2 A/D Converter Control Register (ADCON).......................................................................................14-2 Internal Reference Voltage Levels..................................................................................................14-3 Conversion Timing .......................................................................................................................14-4 Internal A/D Conversion Procedure ................................................................................................14-4 Chapter 15 Electrical Data Overview .............................................................................................................................................15-1 Chapter 16 Mechanical Data Overview .............................................................................................................................................16-1 Chapter 17 S3F880A Overview .............................................................................................................................................17-1 Chapter 18 Development Tools Overview .............................................................................................................................................18-1 Shine .........................................................................................................................................18-1 SAMA Assembler........................................................................................................................18-1 SASM88.....................................................................................................................................18-1 HEX2ROM ..................................................................................................................................18-1 Target Boards .............................................................................................................................18-2 TB880A Target Board...................................................................................................................18-3 S3C880A/F880A MICROCONTROLLER ix List of Figures Figure Number 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-9 2-10 2-12 2-13 2-14 2-15 2-16 2-17 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 4-1 Title Page Number Block Diagram ....................................................................................................1-3 S3C880A/F880A Pin Assignment (42-SDIP) ..........................................................1-4 S3C880A/F880A Pin Assignment (44-QFP)...........................................................1-5 Pin Circuit Type 1 (V-Sync H-Sync, CAPA) ...........................................................1-8 Pin Circuit Type 2 (P2.0-P2.7, P0.0-P0.3, PWM0-PWM5, T0, OSDHT) ..................1-8 Pin Circuit Type 3 (P0.4-P0.5, P1.6-P1.7, T0CK) ..................................................1-8 Pin Circuit Type 4 (Vblue, Vgreen, Vred, Vblank)....................................................1-9 Pin Circuit Type 5 (P1.4-P1.5)..............................................................................1-9 Pin Circuit Type 6 (P3.0-P3.1, P0.6-P0.7, ADC0-ADC3)........................................1-9 Pin Circuit Type 7 (P1.0-P1.3, INT0-INT3).............................................................1-10 Pin Circuit Type 8 (nRESET) ................................................................................1-10 Program Memory Address Spaces........................................................................2-2 Internal Register File Organization.........................................................................2-4 ROM Code Option (RCOD_OPT)...........................................................................2-5 Register Page Pointer (PP) ..................................................................................2-6 Programming Tip Example for Inter-Page Data Operations.......................................2-7 Set 1, Set 2, and Prime Area Register Map ...........................................................2-15 8-Byte Working Register Areas (Slices).................................................................2-16 Contiguous 16-Byte Working Register Block..........................................................2-17 Non-Contiguous 16-Byte Working Register Block ...................................................2-18 16-Bit Register Pairs............................................................................................2-19 Register File Addressing ......................................................................................2-20 Common Working Register Area...........................................................................2-21 4-Bit Working Register Addressing........................................................................2-23 4-Bit Working Register Addressing Example..........................................................2-23 8-Bit Working Register Addressing........................................................................2-24 8-Bit Working Register Addressing Example..........................................................2-25 Stack Operations ................................................................................................2-26 Register Addressing ............................................................................................3-2 Working Register Addressing ...............................................................................3-2 Indirect Register Addressing to Register File..........................................................3-3 Indirect Register Addressing to Program Memory ...................................................3-4 Indirect Working Register Addressing to Register File.............................................3-5 Indirect Working Register Addressing to Program or Data Memory...........................3-6 Indexed Addressing to Register File ......................................................................3-7 Indexed Addressing to Program or Data Memory with Short Offset ...........................3-8 Indexed Addressing to Program or Data Memory ....................................................3-9 Direct Addressing for Load Instructions..................................................................3-10 Direct Addressing for Call and Jump Instructions ....................................................3-11 Indirect Addressing..............................................................................................3-12 Relative Addressing .............................................................................................3-13 Immediate Addressing .........................................................................................3-14 Register Description Format .................................................................................4-5 S3C880A/F880A MICROCONTROLLER xi List of Figures (Continued) Figure Number 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 6-1 7-1 7-2 7-3 7-4 8-1 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 10-1 10-2 10-3 10-4 10-5 10-6 10-7 11-1 11-2 Title Page Number S3C8-Series Interrupt Types .................................................................................5-2 S3C880A/F880A Interrupt Structure ......................................................................5-3 ROM Vector Address Area...................................................................................5-4 Interrupt Function Diagram ...................................................................................5-7 System Mode Register (SYM) ..............................................................................5-9 Interrupt Mask Register (IMR) ...............................................................................5-10 Interrupt Priority Register (IPR) .............................................................................5-11 Interrupt Request Register (IRQ) ...........................................................................5-12 System Flags Register (FLAGS)...........................................................................6-6 Main Oscillator Circuit (External Crystal or Ceramic Resonator)...............................7-1 System Clock Circuit Diagram..............................................................................7-2 System Clock Control Register (CLKCON).............................................................7-3 L-C Oscillator Circuit for OSD...............................................................................7-4 Stop State Timing Diagram...................................................................................8-7 Port Data Register Format....................................................................................9-2 Port 0 High-Byte Control Register (P0CONH) .........................................................9-3 Port 0 Low-Byte Control Register (P0CONL) ..........................................................9-3 Port 1 High-Byte Control Register (P1CONH) .........................................................9-4 Port 1 Low-Byte Control Register (P1CONL) ..........................................................9-4 Port 2 High-Byte Control Register (P2CONH) .........................................................9-5 Port 2 Low-Byte Control Register (P2CONL) ..........................................................9-5 Port 3 Control Register (P3CON)...........................................................................9-6 Basic Timer Control Register (BTCON) ..................................................................10-2 Oscillation Stabilization Time on RESET ...............................................................10-4 Oscillation Stabilization Time on STOP Mode Release............................................10-5 Timer 0 Control Register (T0CON) .........................................................................10-6 Timer 0 Function Diagram (Interval Timer Mode) .....................................................10-7 Timer 0 Function Diagram (PWM Mode) ................................................................10-8 Basic Timer and Timer 0 Block Diagram ................................................................10-9 Timer A Block Diagram ........................................................................................11-2 Timer A Control Register (TACON) ........................................................................11-3 xii S3C880A/F880A MICROCONTROLLER List of Figures (Continued) Figure Number 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 13-17 13-18 13-19 13-20 13-21 13-22 13-23 13-24 13-25 13-26 13-27 13-28 13-29 13-30 13-31 13-32 13-33 Title Page Number PWM Control Register (PWMCON).......................................................................12-2 Block Diagram for PWM2-PWM5 .........................................................................12-3 PWM Waveforms for PWM2-PWM5 .....................................................................12-5 PWM Clock to PWM2-PWM5 Output Delays........................................................12-6 Block Diagram for PWM0 and PWM1....................................................................12-9 Decision Flowchart for PWM0 Programming Tip .....................................................12-10 Block Diagram for Capture A ................................................................................12-12 Decision Flowchart (Main Routine and Timer A Interrupt).........................................12-14 Decision Flowchart for Capture A Interrupt .............................................................12-15 On-Screen Display Function Block Diagram...........................................................13-3 On-Screen Display Video RAM Data Organization..................................................13-4 OSD Display Control Register (DSPCON)..............................................................13-6 OSD Character Size Control Register (CHACON) ...................................................13-8 OSD Character Sizing Dimensions........................................................................13-9 OSD Fade Control Register (FADECON) ...............................................................13-10 Line and Row Addressing Conventions when ROWCON.2-.0 = "100"........................13-11 OSD Fade Function Example: Fade After ..............................................................13-12 OSD Fade Function Example: Fade Before............................................................13-13 252-Byte On-Screen Character Display Map (Decimal) ...........................................13-14 252-Byte On-Screen Character Display Map (Hexadecimal) ....................................13-14 OSD Row Control Register (ROWCON) .................................................................13-15 OSD Column Control Register (CLMCON)..............................................................13-15 OSD Display Formatting and Spacing Conventions .................................................13-16 OSD Character Color Buffer Register (COLBUF).....................................................13-17 Background Color Display Conventions..................................................................13-18 OSD Background Color Control Register (COLCON) ...............................................13-19 V-sync Blank Control Register (VSBCON) .............................................................13-20 V-sync Blank and Top Margin Timing Diagram .......................................................13-21 Halftone Signal Control Register (HTCON)..............................................................13-23 Halftone or Character Backgound Signal Output .....................................................13-24 OSD Field Control Register (OSDFLD) ..................................................................13-25 Field Detect in Before V-sync ...............................................................................13-26 Field Detect in After V-sync..................................................................................13-26 OSD Palette Color Mode Register R1 (OSDPLTR1) ................................................13-27 OSD Palette Color Mode Register R2 (OSDPLTR2) ................................................13-28 OSD Palette Color Mode Register G1 (OSDPLTG1)................................................13-29 OSD Palette Color Mode Register G2 (OSDPLTG2)................................................13-29 OSD Palette Color Mode Register B1 (OSDPLTB1) ................................................13-30 OSD Palette Color Mode Register B2 (OSDPLTB2) ................................................13-30 OSD Space Color Control Register (OSDCOL) .......................................................13-32 OSD Fringe/Border Control Register 1 (OSDFRG1).................................................13-34 OSD Fringe/Border Control Register 2 (OSDFRG2).................................................13-34 S3C880A/F880A MICROCONTROLLER xiii List of Figures (Concluded) Figure Number 13-34 13-35 13-36 13-37 13-38 14-1 14-2 14-3 14-4 14-5 15-1 15-2 15-3 16-1 16-2 17-1 18-1 18-2 18-3 18-4 Title Page Number OSD Smooth Control Register 1 (OSDSMH1) ........................................................13-35 OSD Smooth Control Register 2 (OSDSMH2) ........................................................13-36 Smoothing/Fringing/Priority of Smoothing and Fringing............................................13-36 Decision Flowchart for Row Interrupt Function Programming Tip...............................13-37 Decision Flowchart for Fade Function Programming Tip ..........................................13-40 A/D Converter Control Register (ADCON)...............................................................14-2 A/D Converter Circuit Diagram ..............................................................................14-3 A/D Converter Data Register (ADDATAH/L)............................................................14-3 S3C880A/F880A A/D Converter Timing Diagram.....................................................14-4 Recommended A/D Converter Circuit for Highest Absolute Accuracy........................14-5 Input Timing Measurement Points for tNF1 and tNF2 .................................................15-5 Stop Mode Release Timing When Initiated by a nRESET........................................15-5 Clock Timing Measurement Points for XIN ..............................................................15-6 42-Pin SDIP Package Dimensions (42-SDIP-600)...................................................16-1 44-Pin QFP Package Dimensions (44-QFP-1010B) ................................................16-2 Descriptions of Pins Used to Read/Write the Flash ROM (S3F880A)........................17-2 SMDS Product Configuration (SMDS2+)................................................................18-2 TB880A Target Board Configuration.......................................................................18-3 50-Pin DIP Connector J101 for TB880A..................................................................18-7 S3C880A/F880A Probe Adapter for 42-SDIP Package ............................................18-7 xiv S3C880A/F880A MICROCONTROLLER List of Tables Table Number 1-1 2-1 2-2 4-1 4-2 4-3 5-1 5-2 5-3 6-1 6-2 6-3 6-4 6-5 6-6 8-1 8-2 8-3 9-1 9-2 12-1 12-2 13-1 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 17-1 17-2 17-3 17-4 Title Page Number S3C880A/F880A Pin Descriptions.........................................................................1-5 Program ROM and Character ROM Area by the Font Figure....................................2-3 Register Type Summary.......................................................................................2-3 Set 1 Registers ...................................................................................................4-2 Set 1, Bank 0 Registers .......................................................................................4-2 Set 1, Bank 1 Registers .......................................................................................4-4 S3C880A/F880A Interrupt Vectors ........................................................................5-5 Interrupt Control Register Overview ........................................................................5-6 Interrupt Source Control Registers.........................................................................5-8 Instruction Group Summary ..................................................................................6-2 Flag Notation Conventions ....................................................................................6-8 Instruction Set Symbols.......................................................................................6-8 Instruction Notation Conventions ...........................................................................6-9 Opcode Quick Reference .....................................................................................6-10 Condition Codes ..................................................................................................6-12 Set 1 Register Values after a Reset ......................................................................8-2 Set 1, Bank 0 Register Values after a Reset ..........................................................8-3 Page 1 Video RAM Register Values after a Reset ..................................................8-4 S3C880A/F880A Port Configuration Overview .........................................................9-1 Port Data Register Summary ................................................................................9-2 PWM0 and PWM1 Control and Data Registers ......................................................12-8 PWM Output "Stretch" Values for Extension Registers PWM0EX and PWM1EX.......12-8 OSD Function Block Summary .............................................................................13-1 Absolute Maximum Ratings..................................................................................15-2 D.C. Electrical Characteristics..............................................................................15-2 Input/Output Capacitance.....................................................................................15-4 A.C. Electrical Characteristics..............................................................................15-4 Analog R,G,B Output ...........................................................................................15-4 Data Retention Supply Voltage in Stop Mode.........................................................15-5 Main Oscillator and L-C Oscillator Frequency.........................................................15-6 Main Oscillator Clock Stabilization Time................................................................15-7 A/D Converter Electrical Characteristics ................................................................15-7 Power Selection Settings for TB880A ....................................................................17-4 The SMDS2 + Tool Selection Setting ....................................................................17-5 OSD Font ROM Selection Setting.........................................................................17-5 Using Single Header Pins as the Input Path for External Trigger Sources..................17-6 S3C880A/F880A MICROCONTROLLER xv List of Programming Tips Description Chapter 2: Address Spaces Page Number Data Operations Between Register Pages .........................................................................................2-7 Examples of Inter-Page Data Transfer Operations ...............................................................................2-8 Setting the Register Pointers ............................................................................................................2-17 Using the RPs to Calculate the Sum of a Series of Registers ..............................................................2-18 Addressing the Common Working Register Area ................................................................................2-22 Chapter 5: Interrupt Structure Programming Level IRQ0 as a Fast Interrupt ......................................................................................5-18 Chapter 12: PWM and Capture Programming PWM0 to Sample Specifications ..................................................................................12-10 Programming the Capture Module to Sample Specifications ................................................................12-16 Chapter 13: On-Screen Display (OSD) Row Interrupt Function .....................................................................................................................13-37 Writing Character Code and Color Data to the OSD Video RAM...........................................................13-39 OSD Fade Function; Line and Row Counters .....................................................................................13-39 Manipulating OSD Character Colors; Halftone Function.......................................................................13-43 OSD Character Size, Background Color, and Display Position.............................................................13-45 Helpful Hints About COLBUF and OSD Character Code 0 ...................................................................13-45 Chapter 14: Analog-to-Digital Converter Configuring A/D Converter.................................................................................................................14-5 S3C880A/F880A MICROCONTROLLER xvii List of Register Descriptions Register Identifier ADCON BTCON CHACON CLKCON CLMCON COLBUF COLCON DSPCON EMT FADECON FLAGS HCON IMR IPH IPL IPR IRQ OSDCOL OSDFLD OSDFRG1 OSDFRG2 OSDPLTB1 OSDPLTB2 OSDPLTG1 OSDPLTG2 OSDPLTR1 OSDPLTR2 Full Register Name Page Number A/D Converter Control Register .............................................................................4-6 Basic Timer Control Register ................................................................................4-7 OSD Character Size Control Register....................................................................4-8 System Clock Control Register.............................................................................4-9 OSD Column Control Register ..............................................................................4-10 OSD Character Color Buffer..................................................................................4-11 OSD Background Color Control Register................................................................4-12 On-Screen Display Control Register ......................................................................4-13 External Memory Timing Register .........................................................................4-14 OSD Fade Control Register ..................................................................................4-15 System Flag Register ..........................................................................................4-16 HDLC Control Register.........................................................................................4-17 Interrupt Mask Register .......................................................................................4-18 Instruction Pointer (High Byte) ..............................................................................4-19 Instruction Pointer (Low Byte)...............................................................................4-19 Interrupt Priority Register......................................................................................4-20 Interrupt Request Register....................................................................................4-21 OSD Space Color Control Register........................................................................4-22 OSD Field Control Register ..................................................................................4-23 OSD Fringe/Border Control Register 1...................................................................4-24 OSD Fringe/Border Control Register 2...................................................................4-25 OSD Palette Color Mode Register B1....................................................................4-26 OSD Palette Color Mode Register B2....................................................................4-27 OSD Palette Color Mode Register G1....................................................................4-28 OSD Palette Color Mode Register G2....................................................................4-29 OSD Palette Color Mode Register R1....................................................................4-30 OSD Palette Color Mode Register R2....................................................................4-31 S3C880A/F880A MICROCONTROLLER xix List of Register Descriptions Register Identifier OSDSMH1 OSDSMH2 P0CONH P0CONL P1CONH P1CONL P2CONH P2CONL P3CONH PP PWMCON ROWCON RP0 RP1 SPH SPL STCON SYM TACON T0CON VSBCON Full Register Name (Continued) Page Number OSD Smooth Control Register 1 ...........................................................................4-32 OSD Smooth Control Register 2 ...........................................................................4-33 Port 0 Control Register (High Byte) .......................................................................4-34 Port 0 Control Register (Low Byte) ........................................................................4-35 Port 1 Control Register (High Byte) .......................................................................4-36 Port 1 Control Register (Low Byte) ........................................................................4-37 Port 2 Control Register (High Byte) .......................................................................4-38 Port 2 Control Register (Low Byte) ........................................................................4-39 Port 3 Control Register (High Byte) .......................................................................4-40 Register Page Pointer..........................................................................................4-41 PWM Control Register .........................................................................................4-42 OSD Row Position Control Register ......................................................................4-43 Register Pointer 0................................................................................................4-44 Register Pointer 1................................................................................................4-44 Stack Pointer (High Byte).....................................................................................4-45 Stack Pointer (Low Byte) .....................................................................................4-45 Stop Control Register...........................................................................................4-46 System Mode Register ........................................................................................4-47 8-Bit Timer A Control Register ..............................................................................4-48 Timer 0 Control Register.......................................................................................4-49 V-Sync Blank Control Register .............................................................................4-50 xx S3C880A/F880A MICROCONTROLLER List of Instruction Descriptions Instruction Mnemonic ADC ADD AND BAND BCP BITC BITR BITS BOR BTJRF BTJRT BXOR CALL CCF CLR COM CP CPIJE CPIJNE DA DEC DECW DI DIV DJNZ EI ENTER EXIT IDLE INC INCW IRET JP JR LD LDB Full Register Name Page Number Add with Carry ....................................................................................................6-14 Add....................................................................................................................6-15 Logical AND........................................................................................................6-16 Bit AND..............................................................................................................6-17 Bit Compare........................................................................................................6-18 Bit Complement ..................................................................................................6-19 Bit Reset ............................................................................................................6-20 Bit Set................................................................................................................6-21 Bit OR................................................................................................................6-22 Bit Test, Jump Relative on False...........................................................................6-23 Bit Test, Jump Relative on True.............................................................................6-24 Bit XOR ..............................................................................................................6-25 Call Procedure ....................................................................................................6-26 Complement Carry Flag .......................................................................................6-27 Clear ..................................................................................................................6-28 Complement .......................................................................................................6-29 Compare.............................................................................................................6-30 Compare, Increment, and Jump on Equal...............................................................6-31 Compare, Increment, and Jump on Non-Equal........................................................6-32 Decimal Adjust....................................................................................................6-33 Decrement ..........................................................................................................6-35 Decrement Word .................................................................................................6-36 Disable Interrupts ................................................................................................6-37 Divide (Unsigned).................................................................................................6-38 Decrement and Jump if Non-Zero ..........................................................................6-39 Enable Interrupts .................................................................................................6-40 Enter..................................................................................................................6-41 Exit ....................................................................................................................6-42 Idle Operation......................................................................................................6-43 Increment ...........................................................................................................6-44 Increment Word...................................................................................................6-45 Interrupt Return ...................................................................................................6-46 Jump..................................................................................................................6-47 Jump Relative......................................................................................................6-48 Load...................................................................................................................6-49 Load Bit..............................................................................................................6-51 S3C880A/F880A MICROCONTROLLER xxi List of Instruction Descriptions (Continued) Instruction Mnemonic LDC/LDE LDCD/LDED LDCI/LDEI LDCPD/LDEPD LDCPI/LDEPI LDW MULT NEXT NOP OR POP POPUD POPUI PUSH PUSHUD PUSHUI RCF RET RL RLC RR RRC SB0 SB1 SBC SCF SRA SRP/SRP0/SRP1 STOP SUB SWAP TCM TM WFI XOR Full Register Name Page Number Load Memory ......................................................................................................6-52 Load Memory and Decrement ...............................................................................6-54 Load Memory and Increment ................................................................................6-55 Load Memory with Pre-Decrement ........................................................................6-56 Load Memory with Pre-Increment ..........................................................................6-57 Load Word..........................................................................................................6-58 Multiply (Unsigned)..............................................................................................6-59 Next...................................................................................................................6-60 No Operation.......................................................................................................6-61 Logical OR..........................................................................................................6-62 Pop from Stack ...................................................................................................6-63 Pop User Stack (Decrementing)............................................................................6-64 Pop User Stack (Incrementing) .............................................................................6-65 Push to Stack.....................................................................................................6-66 Push User Stack (Decrementing)..........................................................................6-67 Push User Stack (Incrementing) ...........................................................................6-68 Reset Carry Flag .................................................................................................6-69 Return ................................................................................................................6-70 Rotate Left ..........................................................................................................6-71 Rotate Left through Carry .....................................................................................6-72 Rotate Right........................................................................................................6-73 Rotate Right through Carry ...................................................................................6-74 Select Bank 0.....................................................................................................6-75 Select Bank 1.....................................................................................................6-76 Subtract with Carry ..............................................................................................6-77 Set Carry Flag.....................................................................................................6-78 Shift Right Arithmetic...........................................................................................6-79 Set Register Pointer ............................................................................................6-80 Stop Operation....................................................................................................6-81 Subtract .............................................................................................................6-82 Swap Nibbles ......................................................................................................6-83 Test Complement under Mask ..............................................................................6-84 Test under Mask .................................................................................................6-85 Wait for Interrupt..................................................................................................6-86 Logical Exclusive OR...........................................................................................6-87 xxii S3C880A/F880A MICROCONTROLLER S3C880A/F880A PRODUCT OVERVIEW 1 OVERVIEW PRODUCT OVERVIEW The S3C880A/F880A microcontroller has 48-Kbytes of on-chip program memory. This chips have a 336-byte generalpurpose internal register file. The interrupt structure has 9 interrupt sources with 9 interrupt vectors. The CPU recognizes seven interrupt priority levels. Using a modular design approach, the following peripherals were integrated with the SAM88LP core to make the S3C880A/F880A microcontrollers suitable for use in color television and other types of screen display applications: -- Four programmable I/O ports (26 pins total: 16 general-purpose I/O pins; 10 n-channel, open-drain output pins) -- Four Channel A/D converter (8-bit resolution) -- Two 14-bit PWM output and four 8-bit PWM output. -- Basic timer (BT) with watchdog timer function -- One 8-bit general-purpose timer/counter (T0) with interval timer Mode and PWM Output Mode -- One 8-bit timer/counters (TA) with prescalers and interval timer mode -- On-screen display (OSD) with a wide range of programmable features, including halftone control signal output The S3C880A/F880A is available in a versatile 42-pin SDIP, 44-pin QFP package. 1-1 PRODUCT OVERVIEW S3C880A/F880A FEATURES CPU * SAM88LP CPU core Pulse Width Modulation Module * * * * 14-bit PWM with 2-channel output 8-bit PWM with 4-channel output PWM counter and data capture input pin Frequency: 5.859 kHz to 23.437 kHz with a 6-MHz CPU clock Memory * * 48-Kbyte internal program and OSD font memory 336-byte general-purpose register area Instruction Set * * 78 instructions IDLE and STOP instructions added for power-down modes On-Screen Display (OSD) * * Video RAM: 252 x 14 bits Character generator ROM: Variable size Max:1024 x 18 x 16 bits Min: Default 2 font reserved. (1024 display characters: fixed: 2, variable: 1022) * * * * * * * * * * * 252 display positions (12 rows x 21 columns) 16-dot x 18-dot character resolution 16 different character sizes 64 character colors Fade In/Out 64 colors for character and frame background Halftone control signal output; select able for individual characters Synchronous polarity selector for H-sync and V-sync input Bordering function Smoothing function Fringing function Instruction Execution Time * 750 ns (minimum) with an 8-MHz CPU clock Interrupts * * * 9 interrupt sources with 9 vectors 7 interrupt levels Fast interrupt processing for select levels General I/O * * * Four I/O ports (26 pins total) Six open-drain pins for up to 6-volt loads Four open-drain pins for up to 5-volt loads 8-Bit Basic Timer * * Three select able internal clock frequencies Watchdog or oscillation stabilization function Timer/Counters * One 8-bit timer/counter (T0) with three internal clocks or an external clock, and two operating modes; Interval mode or PWM mode One general-purpose 8-bit timer/counters with interval timer (timer A) Oscillator Frequency * * 5-MHz to 8-MHz external crystal oscillator (when OSD block active) Maximum 8-MHz CPU clock * Operating Temperature Range * - 20C to + 85C A/D Converter * * * Four analog input pins 8-bit resolution 25 us conversion time (8-MHz CPU clock) Operating Voltage Range * 4.5 V to 5.5 V Package Type * 42-pin SDIP, 44-pin QFP 1-2 S3C880A/F880A PRODUCT OVERVIEW BLOCK DIAGRAM P0.0-P0.7 P1.0-P1.7 nRESET Port 0 Port 1 INT0-INT3 Test XIN XOUT Main OSC OSCIN OSCOUT L-C OSC Port I/O and Interrupt Control Timers A H-sync V-sync Vred Vgreen Vblue Vblank OSDHT OnScreen Display Timer 0 CAPA T0 SAM88LP CPU PWM Block PWM Counter and Data Capture CAPA ADC0 ADC1 ADC2 ADC3 8-Bit ADC 48-Kbyte ROM 336-Byte Register File 14-Bit PWM 8-Bit PWM SAM88 Bus PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 Port 2 Port 3 P2.0-P2.7 P3.0-P3.1 Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C880A/F880A PIN ASSIGNMENTS PWM0/P2.5 PWM1/P2.1 PWM2/P2.2 PWM3/P2.3 PWM4/P2.4 PWM5/P2.0 T0/P2.6 T0CK/P1.7 ADC0/P3.0 ADC1/P3.1 ADC2/P0.6 ADC3/P0.7 TEST INT0/P1.0 INT1/P1.1 INT2/P1.2 INT3/P1.3 P1.4 P1.5 P1.6 OSDHT/P2.7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S3C880A S3F880A (42-SDIP) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P0.0 P0.1 P0.2 P0.3 P0.4 VSS CAP.A P0.5 VDD nRESET XOUT XIN VSS1 OSCOUT OSCIN V-sync H-sync Vblank Vred Vgreen Vblue Figure 1-2. S3C880A/F880A Pin Assignment (42-SDIP) 1-4 S3C880A/F880A PRODUCT OVERVIEW P2.0/PWM5 P2.6/T0 P1.7/T0CLK P3.0/ADC0 P3.1/ADC1 P0.6/ADC2 P0.7/ADC3 TEST P1.0/INT0 P1.1/INT1 P1.2/INT2 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 P2.4/PWM4 P2.3/PWM3 P2.2/PWM2 P2.1/PWM1 P2.5/PWM0 P0.0 P0.1 P0.2 P0.3 P0.4 VSS S3C880A S3F880A (44-QFP) 33 32 31 30 29 28 27 26 25 24 23 NC CAP.A P0.5 VDD nRESET XOUT XIN VSS1 NC OSCOUT OSCIN Figure 1-3. S3C880A/F880A Pin Assignment (44-QFP) P1.3/INT3 P1.4 P1.5 P1.6 P2.7/OSDHT Vblue Vgreen Vred Vblank H-sync V-sync 12 13 14 15 16 17 18 19 20 21 22 1-5 PRODUCT OVERVIEW S3C880A/F880A PIN DESCRIPTIONS Table 1-1. S3C880A/F880A Pin Descriptions Pin Name P0.0-P0.3 Pin Type I/O Pin Description General I/O port (4-bit), configurable for digital input or n-channel open-drain, push-pull output. Pins can withstand up to 5-volt loads. General I/O port (2-bit), configurable for digital input or push-pull output. General I/O port (2-bit), configurable for digital input or n-channel open-drain output. P0.6-P0.7 can withstand up to 5-volt loads. Multiplexed for alternative use as external inputs ADC2-ADC3. I/O General I/O port (4-bit), configurable for digital input or n-channel open-drain output. P1.0-P1.3 can withstand up to 6-volt loads. Multiplexed for alternative use as external interrupt inputs INT0-INT3 General I/O port (2-bit). configurable for digital input or n-channel open-drain output. P1.4-P1.5 can withstand up to 6-volt loads. High current port (10mA). General I/O port (2-bit). configurable for digital input or push-pull output. Each pin has an alternative function. P1.7: T0CK (Timer 0 Clock Input) I/O General I/O port (8-bit). Input/output mode or nchannel open-drain, push-pull output mode is software configurable. Pins can withstand up to 5volt loads. Each pin has an alternative function. P2.0: PWM5 (8-bit PWM output) P2.1: PWM1 (14-bit PWM output) P2.2: PWM2 (8-bit PWM output) P2.3: PWM3 (8-bit PWM output) P2.4: PWM4 (8-bit PWM output) P2.5: PWM0 (14-bit PWM output) P2.6: T0 (Timer 0 PWM and Interval output) P2.7: OSDHT (Halftone signal output) General I/O port (2-bit), configurable for digital input or n-channel open-drain output. P3.0-P3.1 can withstand up to 5-volt loads. Multiplexed for alternative use as external inputs ADC0-ADC1. Circuit Type 2 Pin Numbers 39-42 (39-36) 38, 35 (35, 31) 11-12 (6-7) ADC2-ADC3 Share Pins (See pin description) P0.4-P0.5 P0.6-P0.7 3 6 P1.0-P1.3 7 14-17 (9-11) INT0-INT3 P1.4-P1.5 5 18-19 (13-14) P1.6-P1.7 3 20, 8 (15, 3) T0CK P2.0-P2.7 2 PWM0-PWM5 1-7, 21 T0, OSDHT (1, 41-44, 40, 2, 16) P3.0-P3.1 I/O 6 9-10 (4-5) ADC0-ADC1 NOTE: Parentheses indicate pin number for 44-QFP package. 1-6 S3C880A/F880A PRODUCT OVERVIEW Table 1-1. S3C880A/F880A Pin Descriptions (Continued) Pin Name PWM0 PWM1 PWM2-PWM4 PWM5 ADC0-ADC1 ADC2-ADC3 INT0-INT3 T0 T0CK OSDHT Vblue, Vgreen Vred Vblank H-sync, V-sync OSCIN, OSCOUT XIN, XOUT nRESET TEST VDD, VSS CAPA NOTE: Pin Type O O O O I I I O I O O O I I, O I, O I - - I Pin Description Output pin for 14-bit PWM circuit Output pin for 14-bit PWM circuit Output pin for 8-bit PWM circuit Output pin for 8-bit PWM circuit Analog inputs for 8-bit A/D converter Analog inputs for 8-bit A/D converter External interrupt input pins Timer 0 output (interval, PWM) Timer 0 clock input Halftone control signal output for OSD Digital blue, green and red signal outputs for OSD Digital video blank signal outputs for OSD H-sync, V-sync input for OSD L-C oscillator pins for OSD clock frequency generation System clock pins System reset input pin Test Pin (must be connected to VSS). Factory test mode is activated when 12 V is applied. Power supply pins Input for capture A module Circuit Type 1 2 2 2 6 6 7 2 3 2 4 4 1 - - 8 - - 1 Pin Numbers 1 (40) 2 (41) 3-5 (42-44) 6 (1) 9,10 (4,5) 11,12 (6,7) 14-17 (9-11) 7 (2) 8 (3) 21 (16) 22-24 (17-19) 25 (20) 26, 27 (21,22) 28, 29 (23,24) 31, 32 (27,28) 33 (29) 13 (8) 30, 34, 37 (26,30,34) 36 (32) Share Pins P2.5 P2.1 P2.2-P2.4 P2.0 P3.0-P3.1 P0.6-P0.7 P1.0-P1.3 P2.6 P1.7 P2.7 - - - - - - - - - Parentheses indicate pin number for 44-QFP package. 1-7 PRODUCT OVERVIEW S3C880A/F880A PIN CIRCUITS Noise Filter Input Figure 1-4. Pin Circuit Type 1 (V-Sync H-Sync, CAPA) VDD Data I/O Open-Drain Output Disable Input Figure 1-5. Pin Circuit Type 2 (P2.0-P2.7, P0.0-P0.3, PWM0-PWM5, T0, OSDHT) VDD Data Output VSS Input Figure 1-6. Pin Circuit Type 3 (P0.4-P0.5, P1.6-P1.7, T0CK) 1-8 S3C880A/F880A PRODUCT OVERVIEW VDD Data Output VSS Figure 1-7. Pin Circuit Type 4 (Vblue, Vgreen, Vred, Vblank) I/O Data VSS Input Figure 1-8. Pin Circuit Type 5 (P1.4-P1.5) I/O Data VSS Input A/D In NOTE: Circuit type 6 can withstand up to 5 V loads. Figure 1-9. Pin Circuit Type 6 (P3.0-P3.1, P0.6-P0.7, ADC0-ADC3) 1-9 PRODUCT OVERVIEW S3C880A/F880A I/O Data VSS Input INT Noise Filter NOTE: Circuit type 7 can withstand up to 6 V loads. Figure 1-10. Pin Circuit Type 7 (P1.0-P1.3, INT0-INT3) VDD 250 K Noise Filter Figure 1-11. Pin Circuit Type 8 (nRESET) 1-10 S3C880A/F880A ADDRESS SPACES 2 OVERVIEW ADDRESS SPACES The S3C880A/F880A microcontroller has two kinds of address space: -- Internal program memory (ROM) -- Internal register file The S3C880A/F880A has an on-chip 48-Kbyte mask-programmable. There are 336 general-purpose 8-bit data registers in the register file. Seventeen 8-bit registers are used for CPU and system control. To support peripheral, I/O, and clock functions, there are 33 control registers and 16 data registers. In addition, there is a 252 x 4-bit area for on-screen display (OSD) video RAM. 2-1 ADDRESS SPACES S3C880A/F880A PROGRAM MEMORY (ROM) The S3C880A/F880A has a 48-Kbyte mask-programmable program memory. Program memory stores program codes , table data or OSD font codes. As shown in Figure 2-1, the first 256 bytes of the ROM (0H-0FFH) are reserved for interrupt vector addresses. Unused locations in this range can be used as normal program memory. If the vector address area is used to store normal program data, care must be taken to avoid overwriting vector addresses stored in these locations. The ROM address at which program execution starts after a nRESET is 0100H. BFFFH Program Memory and Character Generator Memory 100H Interrupt Vector Area 40H ROM Code Option Area 3CH 0H Figure 2-1. Program Memory Address Spaces 2-2 S3C880A/F880A ADDRESS SPACES Table 2-1. Program ROM and Character ROM Area by the Font Figure Font 0 ROM size ROM address 256 ROM size ROM address 384 ROM size ROM address 512 ROM size ROM address 640 ROM size ROM address 768 ROM size ROM address 1024 ROM size ROM address ROM Program ROM 48-Kbyte 0-BFFFH 39-Kbyte 0-9BFFH 34.5-Kbyte 0-89FFH 30-Kbyte 0-77FFH 25.5-Kbyte 0-65FFH 21-Kbyte 0-53FFH 12-Kbyte 0-2FFFH Character ROM 0-Kbyte 0 9-Kbyte 9C00H-BFFFH 13.5-Kbyte 8A00H-BFFFH 18-Kbyte 7800H-BFFFH 22.5-Kbyte 6600H-BFFFH 27-Kbyte 5400H-BFFFH 36-Kbyte 3000H-BFFFH REGISTER ARCHITECTURE The upper 64 bytes of the S3C880A/F880A internal register file is logically expanded into two 64-byte areas, called set 1 and set 2. The upper 32-byte area of set 1 is divided into two register banks, called bank 0 and bank 1. In addition, two register pages are implemented, called page 0 and page 1. The total addressable register space is thereby expanded from 256 bytes to 654 bytes. The extension of the physical register space into separately addressable areas (sets, banks, and pages) is supported by various addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer (PP). Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2-1. Table 2-2. Register Type Summary Register Type General-purpose registers (including the 16-byte working register common area) CPU and system control registers Peripheral, I/O, and clock control/data registers On-screen display (OSD) video RAM Total Addressable Bytes Number of Bytes 336 17 49 252 654 2-3 ADDRESS SPACES S3C880A/F880A SET 1 BANK 1 FFH BANK 0 E0H DFH D0H CFH C0H C0H BFH E0H FFH FFH SET 2 General purpose registers (indirect address mode) Page 0 FFH FBH Page 1 FFH Page 2 SET 2 OSD registers (indirect address mode) C0H BFH Prime data registers (all address mode) OSD registers (all address mode) 40H 3FH Prime data register area (all address mode) 00H 00H 00H Not used System registers Data register area Display register area (Video RAM) Working registers System and peripheral control registers Figure 2-2. Internal Register File Organization 2-4 S3C880A/F880A ADDRESS SPACES ROM CODE OPTION (RCOD_OPT) The address of RCOD_OPT, from 3CH to 3FH, are ROM code option area. By setting the value of RCOD_OPT, S3C880A/F880A operates optionally. But in S3C880A/F880A, the ROM code option is not available. So RCOD_OPT area can be used as the normal ROM area in S3C880A/F880A. ROM_CODE Option (RCOD_OPT) ROM Address: 3CH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used ROM Address: 3DH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used ROM Address: 3EH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used ROM Address: 3FH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used Figure 2-3. ROM Code Option (RCOD_OPT) 2-5 ADDRESS SPACES S3C880A/F880A REGISTER PAGE POINTER (PP) The SAM88LP architecture supports the logical expansion of the physical 256-byte register file in up to 16 separately addressable register pages. Page addressing is controlled by the register page pointer, PP, DFH. Only two pages are implemented in the S3C880A/F880A microcontrollers: page 0 and page 2 (00H-3FH) are used as general-purpose register space and page 1 contains a 252 x 4-bit area for the on-screen display (OSD) video ROM. As shown in Figure 2-3, when the upper nibble of the PP register is '0000B', the selected destination address is located on page 0. When the upper nibble value is '0001B', page 1 is the selected destination. The lower nibble of the page pointer controls the source register page destination addressing: when the lower nibble is '0000B', page 0 is the selected source register page; when the lower nibble is '0001B', page 1 is the source register page. After a reset, the page pointer's source value (the lower nibble) and the destination value (the upper nibble) are always '0000B', automatically selecting page 0 as both the source and the destination. To select page 1 as the source or destination register page, you must modify the register page pointer values accordingly. Because only page 0, page 1 and page 2 are used in the S3C880A/F880A implementation, only pointer values '0000B', `0001B' and `0010B'' are used. Register Page Pointer (PP) DFH, Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Destination register page seleciton bits: 0000B 0001B 0010B Destination: page 0 Destination: page 1 Destinaton: page 2 Not used for the S3F880A Source register page seleciton bits: 0000B 0001B 0010B Destination: page 0 Destination: page 1 Destination: page 2 Not used for the S3F880A . . . 1111B . . . . . . 1111B . . . Not used for the S3F880A Not used for the S3F880A Figure 2-4. Register Page Pointer (PP) 2-6 S3C880A/F880A ADDRESS SPACES F PROGRAMMING TIP - Data Operations Between Register Pages LD LD * * * PP,#10H 20H,45H ; Destination register page 1, source register page 0 ; Register 20H in page 1 Content of the register 45H ; in page 0 ADD 30H,40H ; Register 30H in page 1 Content of 30H in page 1 ; plus (+) the content of 40H in page 0 + 45H 30H 20H 40H Page 0 Page 1 Figure 2-5. Programming Tip Example for Inter-Page Data Operations EFFECT OF DIFFERENT INSTRUCTIONS FOR INTER-PAGE DATA OPERATIONS The source and the destination pages for data operations between pages differ, depending on which instruction you use. The following programming tip, "Examples of Inter-Page Data Transfer Operations," provides you with a detailed list of various case. 2-7 ADDRESS SPACES S3C880A/F880A F PROGRAMMING TIP - Examples of Inter-Page Data Transfer Operations a) ADC R1,R0 ; R0 - source page ; R1 - destination page ; R2, 40H - source page ; R4 - destination page ; R0 - destination page ; 42H - source page ; 40H - destination page ; 42H, 60H - source page ; 40H - destination page ; 40H - destination page Example 1. b) ADC R4,@R2 R2 contains 40H R0,#0AAH 40H,42H c) ADC d) ADC e) ADC 40H,@42H 42H contains 60H 40H,#02H f) NOTE: ADC The above examples also apply to the instructions ADD, SUB, AND, OR, and XOR. Example 2. a) BAND R0,40H.7 ; 40H - source page ; R0 - destination page ; R0 - source page ; 40H - destination page b) BAND 40H.7,R0 NOTE: The above examples also apply to the instructions BOR, BXOR, and LDB. Example 3. a) BCP R3,44H.7 ; 44H - source page ; R3 - destination page ; R3 - destination page Example 4. NOTE: a) BITC R3.7 The above examples also apply to the instructions BITR and BITS. 2-8 S3C880A/F880A ADDRESS SPACES F PROGRAMMING TIP - Examples of Inter-Page Data Transfer Operations (continued) a) BTJRF SKIP,R6.7 ; R6 - source page Example 5. NOTE: The above example also applies to the instructions BTJRT. Example 6. Example 7. a) CALL a) CLR b) CLR @60H 30H @44H 44H contains 40H ; 60H, 61H - source page ; 30H - destination page ; 44H - source page ; 40H - destination page NOTE: The above examples also apply to the instructions RL, RLC, and SRA. Example 8. a) COM b) COM 03H @44H 44H contains 40H ; 03H - destination page ; 44H - source page ; 40H - destination page NOTE: The above examples also apply to the instructions DEC, INC, RR, and RRC. Example 9. a) CP R1,R0 ; R0 - source page ; R1 - destination page ; R4, 40H - source page ; R2 - destination page ; 42H - source page ; 40H - destination page ; 42H, 44H - source page ; 40H - destination page ; 20H - destination page b) CP R2,@R4 R4 contains 40H 40H,42H c) CP d) CP 40H,@42H 42H contains 44H 20H,#0AAH e) CP NOTE: The above examples also apply to the instructions TCM and TM. 2-9 ADDRESS SPACES S3C880A/F880A F PROGRAMMING TIP - Examples of Inter-Page Data Transfer Operations (Continued) a) CPIJE R3,@R5,SKIP R5 contains 40H ; R5, 40H - source page ; R3 - destination page Example 10. NOTE: The above example also applies to the instruction CPIJNE. Example 11. a) DA b) DA 00H @02H 02H contains 40H 60H @00H 00H contains 48H 01H contains 49H ; 00H - source page ; 02H - source page ; 40H - destination page ; 60H, 61H - destination page ; 00H, 01H - source page ; 48H, 49H - destination page Example 12. a) DECW b) DECW NOTE: The above example also applies to the instruction INCW. Example 13. a) DIV 60H,40H ; 40H - source page ; 60H, 61H - destination page ; 20H, 40H - source page ; 60H, 61H - destination page ; 60H, 61H - destination page b) DIV 60H,@20H 20H contains 40H 60H,#03H c) DIV NOTE: The above example also applies to the instruction INCW. Example 14. NOTE: a) DJNZ R6,LOOP ; R6 - destination page Incase PP = 10H, 11H, this instruction is not valid. Example 15. a) JP @60H ; 60H, 61H - source page 2-10 S3C880A/F880A ADDRESS SPACES F PROGRAMMING TIP - Examples of Inter-Page Data Transfer Operations (Continued) a) LD b) LD R0,#0AAH R0,40H ; R0 - destination page ; 40H - source page ; R0 - destination page ; R0 - source page ; 40H - destination page ; R2, 50H - source page ; R0 - destination page ; R4, R2 - source page ; 40H - destination page ; 41H - source page ; 40H - destination page ; 42H, 44H - source page ; 40H - destination page ; 45H - destination page ; 40H - source page ; 44H - destination page ; 40H, 42H - source page ; 44H - destination page ; R0, 04H(2 + offset) - source page ; R5 - destination page ; R0, R1 - source page ; 04H - destination page Example 16. c) LD 40H,R0 d) LD R0,@R2 R2 contains 50H @R4,R2 R4 contains 40H 40H,41H e) LD f) LD g) LD 40H,@42H 42H contains 44H 45H,#02H @40H,#02H 40H contains 44H @40H,42H 40H contains 44H R5,#04H(R0) R0 contains 02H #04H(R0),R1 R0 contains 02H h) LD i) LD j) LD k) LD l) LD 2-11 ADDRESS SPACES S3C880A/F880A F PROGRAMMING TIP - Examples of Inter-Page Data Transfer Operations (Continued) a) LDC R0,@RR6 ; R6, R7 - source page ; R0 - destination page Example 17. b) LDC @RR6,R2 ; R6, R7, R2 - source page RR6 contains an external memory address R0,#01H(RR6) ; R6, R7 - source page ; R0 - destination page ; R0, R6, R7 - source page ; R6, R7 - source page ; R0 - destination page ; R0, R6, R7 - source page c) LDC d) LDC e) LDC #01H(RR6),R0 R0,#1000H(RR6) f) LDC #1000H(RR6),R0 Example 18. a) LDCD R0,@RR6 ; R6, R7 - source page ; R0 - destination page ; R0, R6, R7 - source page b) LDCPD NOTE: @RR6,R0 The above examples also apply to the instructions LDCI and LDCPI. Example 19. a) LDW 40H,20H ; 20H, 21H - source page ; 40H, 41H - destination page ; 20H, 40H - source page ; 60H, 61H - destination page ; 40H, 41H - destination page b) LDW 60H,@20H 20H contains 40H 40H,#02H c) LDW 2-12 S3C880A/F880A ADDRESS SPACES F PROGRAMMING TIP - Examples of Inter-Page Data Transfer Operations (Concluded) a) MULT 40H,20H ; 20H - source page ; 40H, 41H - destination page ; 20H, 40H - source page ; 60H, 61H - destination page ; 40H, 41H - destination page ; 00H - destination page ; 20H - source page ; 40H - destination page 20H, 40H - source page ; 00H - destination page Example 20. b) MULT 60H,@20H 20H contains 40H 40H,#02H 00H @20H 20H contains 40H c) MULT Example 21. a) POP b) POP Example 22. a) POPUD 00H,@20H ; 20H contains 40H NOTE: The above example also applies to the instruction POPUI. Example 23. a) PUSH b) PUSH 00H @20H 20H contains 40H @60H,20H 60H contains 44H ; 00H - destination page ; 20H, 40H - source page Example 24. a) PUSHUD ; 60H, 20H - source page ; 44H - destination page NOTE: The above example also applies to the instruction PUSHUI. Example 25. a) SWAP b) SWAP 00H @20H 20H contains 40H ; 00H - destination page ; 20H - source page ; 40H - destination page 2-13 ADDRESS SPACES S3C880A/F880A REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H-FFH. This area can be accessed at any time, regardless of which page is currently selected. The upper 32-byte area of this 64-byte space is divided into two 32-byte register banks, called bank 0 and bank 1. You use the select register bank instructions, SB0 or SB1, to address one bank or the other. A reset operation automatically selects bank 0 addressing. The lower 32-byte area of set 1 is not banked. This area contains 16 bytes for mapped system registers (D0H-DFH) and a 16-byte common area (C0H-CFH) for working register addressing. Registers in set 1 are directly accessible at all times using Register addressing mode. The 16-byte working register area ,however, can only be accessed using working register addressing. Working register addressing is a function of Register addressing mode (see Chapter 3, "Addressing Modes," for more information). REGISTER SET 2 The same 64-byte physical space that is used for the set 1 register locations C0H-FFH is logically duplicated to add another 64 bytes. This expanded area of the register file is called set 2. The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions: while you can access set 1 using Register addressing mode only, you should use Register Indirect addressing mode or Indexed addressing mode to access set 2. For the S3C880A/F880A, the set 2 address range (C0H-FFH) is accessible on page 0 and page 1. Please note, however, that on page 1, the set 2 locations FCH-FFH are not mapped. Part of the OSD video RAM is in page 1, set 2 (C0H-FBH), and the other part (00H-BFH) is in the page 1 prime register area. To avoid programming errors, we recommend using either Register Indirect or Indexed mode to address the entire 252-byte video RAM area. PRIME REGISTER SPACE The lower 192 bytes (00H-BFH) of the S3C880A/F880A 's two 256-byte register pages and the 64 bytes (00H-3FH) of register page 2 are called prime register area. Prime registers can be accessed using any of the seven addressing modes. The prime register area on page 0 is immediately addressable after a reset. In order to address registers on page 1 (in the OSD video RAM), you must first set the register page pointer (PP) to the appropriate source and destination values. 2-14 S3C880A/F880A ADDRESS SPACES Set 1 Bank 0 FFH FCH E0H D0H C0H C0H C0H Set 2 Set 2 Set 2 Bank 1 FFH Page 0 FFH FBH Page 1 FFH Page 2 CPU and system control General-purpose Peripheral and I/O OSD video RAM Area not mapped 00H 00H 00H Prime Space Prime Space 3FH Prime Space Figure 2-6. Set 1, Set 2, and Prime Area Register Map 2-15 ADDRESS SPACES S3C880A/F880A WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file is viewed as thirty two 8-byte register groups or "slices." Each slice consists of eight 8-bit registers. When the two 8-bit register pointers, RP1 and RP0, are used, two working register slices can be selected at any time to form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block anywhere in the addressable register file (except for the set 2 area). The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces: -- One working register slice is 8 bytes (eight 8-bit working registers; R0-R7 or R8-R15) -- One working register block is 16 bytes (sixteen 8-bit working registers; R0-R15) All the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file. The base addresses for the two selected 8-byte register slices are contained in the register pointers, RP0 and RP1. After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H-CFH). Slice 32 11111XXX RP1 (Registers R8-R15) Each register pointer points to one 8-byte slice of the register space, selecting a total 16-byte working register block in total. FFH F8H F7H F0H Set 1 Only CFH C0H ~ 00000XXX RP0 (Registers R0-R7) Slice 1 ~ 10H FH 8H 7H 0H Figure 2-7. 8-Byte Working Register Areas (Slices) 2-16 S3C880A/F880A ADDRESS SPACES USING THE REGISTER POINTERS The register pointers, RP0 and RP1, are mapped to the addresses D6H and D7H in set 1. They are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to the addresses C0H-C7H, and RP1 points to the addresses C8H-CFH. If you want to change a register pointer value, you should load a new value to RP0 and/or RP1 using an SRP or LD instruction (see Figures 2-7 and 2-8). With working register addressing, you can only access those locations that are pointed to by the register pointers. Please note that you cannot use the register pointers to select the working register area in set 2, C0H-FFH, because these locations are accessible only using the Indirect Register or Indexed addressing mode. The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general programming guideline, we recommend that RP0 point to the "lower" slice and RP1 point to the "upper" slice (see Figure 2-7). In some cases, it may be necessary to define working register areas in different (non-contiguous) areas of the register file. In Figure 2-8, RP0 points to the "upper" slice and RP1 to the "lower" slice. Because a register pointer can point to either of the two 8-byte slices in the working register block, you can flexibly define the working register area. F PROGRAMMING TIP -- Setting the Register Pointers SRP SRP1 SRP0 CLR LD #70H #48H #0A0H RP0 RP1,#0F8H ; ; ; ; ; RP0 RP0 RP0 RP0 RP0 70H, RP1 78H no change, RP1 48H A0H, RP1 no change 00H, RP1 no change no change, RP1 0F8H Register File Contains 32 8-Byte Slices 00001XXX RP1 00000XXX RP0 8-Byte Slice 8-Byte Slice FH (R15) 8H 7H 0H (R0) 16-byte contiguous working register block Figure 2-8. Contiguous 16-Byte Working Register Block 2-17 ADDRESS SPACES S3C880A/F880A F7H (R7) 8-Byte Slice F0H (R0) 11110XXX RP0 00000XXX RP1 Register File Contains 32 8-Byte Slices 16-byte contiguous working register block 7H (R15) 0H (R0) 8-Byte Slice Figure 2-9. Non-Contiguous 16-Byte Working Register Block F PROGRAMMING TIP -- Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of the registers, 80H-85H, using the register pointer. The register addresses 80H through 85H contain the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively: SRP0 ADD ADC ADC ADC ADC #80H R0,R1 R0,R2 R0,R3 R0,R4 R0,R5 ; ; ; ; ; ; RP0 80H R0 R0 + R0 R0 + R0 R0 + R0 R0 + R0 R0 + R1 R2 R3 R4 R5 + + + + C C C C The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles. If you do not use the register pointer to calculate the sum of these registers, you would have to execute the following instruction sequence: ADD ADC ADC ADC ADC 80H,81H 80H,82H 80H,83H 80H,84H 80H,85H ; ; ; ; ; 80H 80H 80H 80H 80H (80H) (80H) (80H) (80H) (80H) + + + + + (81H) (82H) (83H) (84H) (85H) + + + + C C C C Here, the sum of the six registers is also located in the register 80H. This instruction string, however, takes 15 bytes of instruction code rather than 12 bytes, and the execution time is 50 cycles rather than 36 cycles. 2-18 S3C880A/F880A ADDRESS SPACES REGISTER ADDRESSING The SAM8 register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, can be used to access any location in the register file except for set 2. For working register addressing, the register pointers, RP0 and RP1, are used to select a specific register within a selected 16-byte working register area. To increase the speed of context switches in an application program, the register pointers can be used to dynamically select different 8-byte "slices" of the register file as the active working register space. Registers are addressed either as a single 8-bit register or a paired 16-bit register. In 16-bit register pairs, the address of the first 8-bit register is always an even number and that of the next register is an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register. MSB Rn LSB Rn+1 n = Even address Figure 2-9. 16-Bit Register Pairs 2-19 ADDRESS SPACES S3C880A/F880A Special-Purpose Registers Set 1 FFH Bank 1 Bank 0 Control Registers System Registers CFH C0H BFH D7H D6H RP1 Register Pointers RP0 Each register pointer (RP) can independently point to one of the twenty 8-byte "slices" of the register file (other than set 2). After a reset, RP0 points to locations C0H-C7H and RP1 to locations C8H-CFH (the common working register area). General-Purpose Registers FFH Set 2 D0H C0H Prime Registers 00H Page 0, 1 Register Addressing Only All Addressing Modes Page 0, 1 Indirect Register, Indexed Addressing Modes Can be Pointed by Register Pointer Figure 2-11. Register File Addressing 2-20 S3C880A/F880A ADDRESS SPACES COMMON WORKING REGISTER AREA (C0H-CFH) After a reset, the register pointers, RP0 and RP1, automatically point to two 8-byte register slices in set 1, locations C0H-CFH, as the active 16-byte working register block: RP0 C0H-C7H RP1 C8H-CFH This 16-byte address range is a common area. That is, locations in this area can be accessed using working register addressing only. Set 1 FFH FCH E0H DFH CFH C0H C0H BFH FFH Page 0 FFH FBH Set 2 Page 1 Not used FFH Page 2 Set 2 C0H BFH ~ Not used ~ Register pointers RP0 and RP1 point to the common working register area (COH-CFH) after a reset. ~ Prime Area ~ ~ Prime Area ~ 3FH Prime Area RP0 = RP1 = 1100 1100 0000 1000 00H 00H 00H Figure 2-12. Common Working Register Area 2-21 ADDRESS SPACES S3C880A/F880A F PROGRAMMING TIP - Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H-CFH, using working register addressing mode only. Examples: 1. LD 0C2H,40H ; Invalid addressing mode! Use working register addressing instead: SRP LD 2. ADD #0C0H R2,40H 0C3H,#45H ; R2 (C2H) the value in location 40H ; Invalid addressing mode! Use working register addressing instead: SRP ADD #0C0H R3,#45H ; R3 (C3H) R3 + 45H 4-BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8-byte slice of working register space. The address information stored in a register pointer serves as an addressing "window" that enables instructions to access working registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address: -- The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0; "1" selects RP1); -- The five high-order bits in the register pointer select an 8-byte slice of the register space; -- The three low-order bits of the 4-bit address select one of the eight registers in the slice. As shown in Figure 2-12, the net effect of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form a complete address. As long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice. Figure 2-13 shows a typical example of 4-bit working register addressing: the high-order bit of the instruction 'INC R6' is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B). 2-22 S3C880A/F880A ADDRESS SPACES RP0 RP1 Selects RP0 or RP1 Address OPCODE Register pointer provides five high-order bits 4-bit address procides three low-order bits Together they create an 8-bit register address Figure 2-13. 4-Bit Working Register Addressing RP0 01110 000 Selects RP0 RP1 01111 000 01110 110 Register address (76H) R6 0110 OPCODE 1110 Instruction: 'INC R6' Figure 2-14. 4-Bit Working Register Addressing Example 2-23 ADDRESS SPACES S3C880A/F880A 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. In order to initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value 1100B. This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working register addressing. As shown in Figure 2-14, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit addressing: bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address, and the three low-order bits of the complete address are provided by the original instruction. Figure 2-15 shows an example of 8-bit working register addressing: the four high-order bits of the instruction address (1100B) specify 8-bit working register addressing. The fourth bit ("1") selects RP1 and the five high-order bits in RP1 (10100B) become the five high-order bits of the register address. The three low-order bits of the register address (011) are provided by the three low-order bits of the 8-bit instruction address. Together, the five address bits from RP1 and the three address bits from the instruction comprise the complete register address, R163 (10100011B). RP0 RP1 Selects RP0 or RP1 Address These address bits indicate 8-bit working register addressing 8-bit logical address 1 1 0 0 Register pointer provides five high-order bits Three loworder bits 8-bit physical address Figure 2-15. 8-Bit Working Register Addressing 2-24 S3C880A/F880A ADDRESS SPACES RP0 01100 000 Selects RP1 RP1 10101 000 R11 1100 1 011 8-bit address form instruction 'LD R11, R2' 10101 011 Register address (0ABH) Specifies working register addressing Figure 2-16. 8-Bit Working Register Addressing Example 2-25 ADDRESS SPACES S3C880A/F880A SYSTEM AND USER STACKS The S3C8-series microcontrollers use the system stack for subroutine calls and returns, interrupt processing, and data storage. The PUSH and POP instructions support system stack operations. Stack operations in the internal register file and in external data memory are supported by hardware. (The S3C880A/F880A do not support an external memory access.) Bit 1 in the external memory timing register EMT selects an internal or external stack area. The 16-bit stack pointer register (SPH, SPL) is used to access an externally defined system stack. An 8-bit stack pointer (SPL) is sufficient for internal stack addressing. Stack Operations Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by an RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address is always decremented before a push operation and incremented after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-16. High Address PCL PCL Top of stack PCH PCH Top of stack Flags Stack contects after an interrupt Stack contects after a call instruction Low Address Figure 2-17. Stack Operations User-Defined Stacks You can freely define stacks in the internal register file as data storage locations. The instructions, PUSHUI, PUSHUD, POPUI, and POPUD, support user-defined stack operations. Stack Pointers (SPL, SPH) The register locations D8H and D9H contain the 16-bit stack pointer (SP) value. The most significant byte of a 16-bit stack address is stored in the SPH register (D8H) and the least significant byte is stored in the SPL register (D9H). Because an external memory interface is not implemented for the S3C880A/F880A microcontrollers, a single 8-bit stack pointer (SPL) is sufficient to address stack locations in the internal register file. After a reset, the stack pointer value is undetermined. The SPL register must then be initialized to an 8-bit value in the range 00H-FFH, page 0. You can use the SPH register as a general-purpose data register. Please note that when you do so, data stored in SPH may be overwritten if an overflow or underflow of the SPL register occurs during normal stack operations. To prevent this, you can initialize the SPL value to FFH instead of 00H. 2-26 S3C880A/F880A ADDRESS SPACES F PROGRAMMING TIP - Standard Stack Operations Using PUSH and POP The following sample code shows how to perform stack operations in the internal register file using PUSH and POP instructions: LD * * * SPL,#0FFH ; SPL FFH (Normally, the SPL is set to 0FFH by the ; initialization routine) PUSH PUSH PUSH PUSH * * * PP RP0 RP1 R3 ; ; ; ; Stack address 0FEH Stack address 0FDH Stack address 0FCH Stack address 0FBH PP RP0 RP1 R3 POP POP POP POP R3 RP1 RP0 PP ; ; ; ; R3 Stack address 0FBH RP1 Stack address 0FCH RP0 Stack address 0FDH PP Stack address 0FEH 2-27 ADDRESS SPACES S3C880A/F880A NOTES 2-28 S3C880A/F880A ADDRESSING MODES 3 OVERVIEW -- Register (R) ADDRESSING MODES Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is used to determine the location of the data operand. The operands specified in SAM87 instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. The SAM87 instruction set supports seven explicit addressing modes. Not all of these addressing modes are available for each instruction. The addressing modes and their symbols are as follows: -- Indirect Register (IR) -- Indexed (X) -- Direct Address (DA) -- Indirect Address (IA) -- Relative Address (RA) -- Immediate (IM) 3-1 ADDRESSING MODES S3C880A/F880A REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing as it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2). Program Memory 8-bit Register File Address One-Operand Instruction (Example) Register File dst OPCODE OPERAND Point to One Register in Register File Value used in Instruction Execution Sample Instruction: DEC CNTR ; Where CNTR is the label of an 8-bit register address Figure 3-1. Register Addressing Register File MSB Point to RP0 ot RP1 RP0 or RP1 Selected RP points to start of working register block OPERAND Program Memory 4-bit Working Register Two-Operand Instruction (Example) Sample Instruction: ADD R1, R2 3 LSBs Point to the Working Register (1 of 8) dst src OPCODE ; Where R1 and R2 are registers in the curruntly selected working register area. Figure 3-2. Working Register Addressing 3-2 S3C880A/F880A ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, program memory (ROM), or an external memory space (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location. You cannot, however, access the locations C0H-FFH in set 1 using Indirect Register addressing mode. Program Memory 8-bit Register File Address One-Operand Instruction (Example) Register File dst OPCODE Point to One Register in Register File Address of Operand used by Instruction ADDRESS Value used in Instruction Execution OPERAND Sample Instruction: RL @SHIFT ; Where SHIFT is the label of an 8-bit register address Figure 3-3. Indirect Register Addressing to Register File 3-3 ADDRESSING MODES S3C880A/F880A INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory Example Instruction References Program Memory Register Pair Points to Register Pair 16-Bit Address Points to Program Memory dst OPCODE Program Memory Sample Instructions: CALL JP @RR2 @RR2 Value used in Instruction OPERAND Figure 3-4. Indirect Register Addressing to Program Memory 3-4 S3C880A/F880A ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Program Memory 4-Bit Working Register Address 3 LSBs Point to the Working Register (1 of 8) ADDRESS dst src Selected RP Points to Start of Working Register Block OPCODE Sample Instruction: OR R3, @R6 Value used in Instruction OPERAND Figure 3-5. Indirect Working Register Addressing to Register File 3-5 ADDRESSING MODES S3C880A/F880A INDIRECT REGISTER ADDRESSING MODE (Concluded) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to Start of Working Register Block Program Memory 4-bit Working Register Address dst src OPCODE Next 2-bit Point to Working Register Pair (1 of 4) LSB Selects REGISTER PAIR Example Instruction References either Program Memory or Data Memory Program Memory or Data Memory 16-Bit Address Points to Program Memory or Data Memory Value used in Instruction OPERAND Sample Instructions: LCD LDE LDE R5,@RR6 R3,@RR14 @RR4, R8 ; Program memory access ; External data memory access ; External data memory access Figure 3-6. Indirect Working Register Addressing to Program or Data Memory 3-6 S3C880A/F880A ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during the instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. You cannot, however, access the locations C0H-FFH in set 1 using Indexed addressing mode. In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range - 128 to + 127. This applies to external memory accesses only (see Figure 3-8). For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address (see Figure 3-9). The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory, when implemented. Register File RP0 or RP1 Value used in Instruction OPERAND Selected RP Points to Start of Working Register Block + Program Memory Two-Operand Instruction Example Base Address dst/src x OPCODE 3 LSBs Point to One of the Working Register (1 of 8) INDEX Sample Instruction: LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value Figure 3-7. Indexed Addressing to Register File 3-7 ADDRESSING MODES S3C880A/F880A INDEXED ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Program Memory 4-bit Working Register Address OFFSET dst/src x OPCODE NEXT 2 BITS Point to Working Register Pair (1 of 4) REGISTER PAIR Selected RP Points to Start of Working Register Block LSB Selects + 8-Bits 16-Bits Program Memory or Data Memory 16-Bit Address Added to Offset 16-Bits Sample Instructions: LDC LDE R4, #04H[RR2] R4,#04H[RR2] OPERAND Value used in Instruction ; The values in the program address (RR2 + 04H) are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed. Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset 3-8 S3C880A/F880A ADDRESSING MODES INDEXED ADDRESSING MODE (Concluded) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP Points to Start of Working Register Block Program Memory OFFSET OFFSET dst/src src OPCODE 4-bit Working Register Address NEXT 2 BITS Point to Working Register Pair REGISTER FAIR LSB Selects + 8-Bits 16-Bits Program Memory or Data Memory 16-Bit Address Added to Offset 16-Bits Sample Instructions: LDC LDE R4, #1000H[RR2] R4,#1000H[RR2] OPERAND Value used in Instruction ; The values in the program address (RR2 + 1000H) are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed. Figure 3-9. Indexed Addressing to Program or Data Memory 3-9 ADDRESSING MODES S3C880A/F880A DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed. The LDC and LDE instructions can use Direct Address mode to specify the source or the destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented. Program or Data Memory Program Memory Memory Address Used Upper Address Byte Lower Address Byte dst/src "0" or "1" OPCODE LSB Selects Program Memory or Data Memory: "0" = Program Memory "1" = Data Memory Sample Instructions: LDC LDE R5,1234H; The values in the program address (1234H) are loaded into register R5. R5,1234H; Identical operation to LDC example, except that external program memory is accessed. Figure 3-10. Direct Addressing for Load Instructions 3-10 S3C880A/F880A ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions: JP CALL C,JOB1 DISPLAY ; Where JOB1 is a 16-bit immediate address ; Where DISPLAY is a 16-bit immediate address Figure 3-11. Direct Addressing for Call and Jump Instructions 3-11 ADDRESSING MODES S3C880A/F880A INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address located in the lower 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed. Only the CALL instruction can use Indirect Address mode. As Indirect Address mode assumes that the operand is located in the lower 256 bytes of the program memory, only an 8-bit address is provided in the instruction; the upper bytes of the destination address are assumed to be all zeros. Program Memory Next Instruction LSB Must be Zero Current Instruction dst OPCODE Lower Address Byte Upper Address Byte Program Memory Locations 0-255 Sample Instruction: CALL #40H ; The 16-bit value in program memory addresses 40H and 41H is the subroutine start address. Figure 3-12. Indirect Addressing 3-12 S3C880A/F880A ADDRESSING MODES RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between - 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction. Several program control instructions use Relative Address mode to perform conditional jumps. The instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR. Program Memory Next OPCODE Program Memory Address Used Current Instruction Displacement OPCODE Current PC Value + Signed Displacement Value Sample Instructions: JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128 Figure 3-13. Relative Addressing 3-13 ADDRESSING MODES S3C880A/F880A IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers. Program Memory OPERAND OPCODE (The Operand value is in the instruction) Sample Instruction: LD R0,#0AAH Figure 3-14. Immediate Addressing 3-14 S3C880A/F880A CONTROL REGISTERS 4 OVERVIEW CONTROL REGISTERS In this chapter, detailed descriptions of the S3C880A/F880A control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing application programs. System and peripheral registers are summarized in Tables 4-1, 4-2, and 4-3. Figure 4-1 illustrates the important features of the standard register description format. Control register descriptions are arranged in alphabetical order according to register mnemonic. More information about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this manual. 4-1 CONTROL REGISTERS S3C880A/F880A Table 4-1. Set 1 Registers Register Name Timer 0 counter Timer 0 data register Timer 0 control register Basic timer control register Clock control register System flags register Register pointer 0 Register pointer 1 Stack pointer (high byte) Stack pointer (low byte) Instruction pointer (high byte) Instruction pointer (low byte) Interrupt request register Interrupt mask register System mode register Register page pointer Mnemonic T0CNT T0DATA T0CON BTCON CLKCON FLAGS RP0 RP1 SPH SPL IPH IPL IRQ IMR SYM PP Decimal 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 Hex D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W Table 4-2. Set 1, Bank 0 Registers Register Name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 0 control register (high byte) Port 0 control register (low byte) Port 1 control register (high byte) Port 1 control register (low byte) Port 2 control register (high byte) Port 2 control register (low byte) Mnemonic P0 P1 P2 P3 P0CONH P0CONL P1CONH P1CONL P2CONH P2CONL Decimal 224 225 226 227 228 229 230 231 232 233 Hex E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Location EAH in set 1, bank 0, are not mapped. Port 3 control register (low byte) P3CONL 235 EBH R/W Locations ECH - EEH in set 1, bank 0, are not mapped. PLL control register (note) NOTE: PLLCON 236 EFH R/W PLL control register, PLLCON, is a system register for factory test. So user should not access this register. 4-2 S3C880A/F880A CONTROL REGISTERS Table 4-2. Set 1, Bank 0 Registers (Continued) Register Name Timer A data register Mnemonic TADATA Decimal 240 Hex F0H R/W R/W Location F1H in set 1, bank 0, are not mapped. STOP control register Timer A control register PWM0 data register (main byte) PWM0 data register (extension byte) PWM1 data register (main byte) PWM1 data register (extension byte) PWM control register Capture A data register A/D converter control register A/D conversion data register Test control register Basic timer counter External memory timing register Interrupt priority register NOTE: STCON TACON PWM0 PWM0EX PWM1 PWM1EX PWMCON CAPA ADCON ADDATA TSTC BTCNT EMT IPR 238 242 244 245 246 247 248 249 250 251 252 253 254 255 F3H F2H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH R/W R/W R/W R/W R/W R/W R/W R R/W (2) R R/W (1) R R/W R/W Test control register, TSTC, is a system register for factory test. So user should not access this register. 4-3 CONTROL REGISTERS S3C880A/F880A Table 4-3. Set 1, Bank 1 Registers Register Name OSD fringe/border control register 1 OSD fringe/border control register 2 OSD smooth control register 1 OSD smooth control register 2 OSD space color control register OSD field control register OSD palette color mode R 1 OSD palette color mode R 2 OSD palette color mode G 1 OSD palette color mode G 2 OSD palette color mode B 1 OSD palette color mode B 2 Mnemonic OSDFRG1 OSDFRG2 OSDSMH1 OSDSMH2 OSDCOL OSDFLD OSDPLTR1 OSDPLTR2 OSDPLTG1 OSDPLTG2 OSDPLTB1 OSDPLTB2 Decimal 224 225 226 227 236 237 230 231 232 233 234 235 Hex E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Locations ECH-EFH in set 1, bank 1, are not mapped. OSD character size control register OSD fade control register OSD row position control register OSD column position control register OSD background color control register On-screen display control register Halftone signal control register V-SYNC blank control register PWM2 Data register PWM3 Data register PWM4 Data register PWM5 Data register OSD Color Buffer CHACON FADECON ROWCON CLMCON COLCON DSPCON HTCON VSBCON PWM2 PWM3 PWM4 PWM5 COLBUF 240 241 242 243 244 245 246 251 247 248 249 250 252 F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Locations FDH-FFH in set 1, bank 1, are not mapped. 4-4 S3C880A/F880A CONTROL REGISTERS Bit number(s) that is/are appended to the register name for bit addressing Register mnemonic Name of an individual bit or bit function Register address (hexadecimal) Full register name Register location in the internal register file FLAGS -- System Flags Register Bit Identifier .7 .6 .5 .4 .3 x R/W D5H .2 x R/W .1 0 R/W Set 1 .0 0 R/W x x x x RESET Value Read/Write R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Carry Flag (C) 0 1 .6 Operation does not generate a carry or borrow condition Operation generates a carry-out or a borrow condition in high-order bit 7 Zero Flag (Z) 0 1 Operation result is a non-zero value Operation result is zero .5 Sign Flag (S) 0 1 Operation generates a positive number (MSB = "0") Operation generates a negative number (MSB = "1") R W R/W '-' = = = = Read-only Write-only Read/write Not used Description of the effect of specific bit settings RESET value notation: '-' = Not used 'x' = Undetermined value '0' = Logic zero '1' = Logic one Bit number: MSB = Bit 7 LSB = Bit 0 Addressing mode or modes you can use to modify register values Figure 4-1. Register Description Format 4-5 CONTROL REGISTERS S3C880A/F880A ADCON -- A/D Converter Control Register Bit Identifier nRESET Value Read/Write Addressing Mode .7 - - .6 - - .5 0 R/W .4 0 R/W .3 x R FAH .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only .7-.6 Not used for the S3C880A/F880A .5-.4 A/D Converter Input Pin Selection Bits 0 0 1 1 0 1 0 1 ADC0 (P3.0) ADC1 (P3.1) ADC2 (P0.6) ADC3 (P0.7) .3 End-of-Conversion Status Bit (Read Only) 0 1 A/D conversion is in progress A/D conversion complete .2 and .1 Clock Source Selection Bits 0 0 1 1 0 1 0 1 fosc/16 (fosc < 8 MHz) fosc/8 (fosc < 8 MHz) fosc/14(fosc < 8 MHz) fosc/2 (fosc < 8 MHz) .0 Conversion Start Bit 0 0 No meaning A/D conversion start 4-6 S3C880A/F880A CONTROL REGISTERS BTCON -- Basic Timer Control Register Bit Identifier nRESET Value Read/Write Addressing Mode .7-.4 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W D3H .2 0 R/W .1 0 R/W Set 1 .0 0 R/W Register addressing mode only Watchdog Timer Function Disable Code (for Reset) 1 0 1 0 Disable watchdog timer function Enable watchdog timer function Others .3 and .2 Basic Timer Input Clock Selection Bits 0 0 1 1 0 1 0 1 fOSC/4096 fOSC/1024 fOSC/128 Invalid selection .1 Basic Timer Counter Clear Bit (note) 0 1 No effect Clear the basic timer counter value .0 Clock Divider Clear Bit for Basic Timer and Timer 0 (note) 0 1 No effect Clear both dividers NOTE: When you write a "1" to bit 0 or bit 1, the corresponding divider or counter value is cleared to '00H'. The corresponding BTCON bit is then automatically reset by hardware to "0". 4-7 CONTROL REGISTERS S3C880A/F880A CHACON -- OSD Character Size Control Register Bit Identifier nRESET Value Read/Write Addressing Mode .7 and .6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W F0H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only Vertical Character Size Selection Bits 0 0 1 1 0 1 0 1 Select 'x1' vertical character size Select 'x2' vertical character size Select 'x3' vertical character size Select 'x4' vertical character size .5 and .4 Horizontal Character Size Selection Bits 0 0 1 1 0 1 0 1 Select 'x1' horizontal character size Select 'x2' horizontal character size Select 'x3' horizontal character size Select 'x4' horizontal character size .3-.0 Fade Row Address Selection for Rows 0-11 in On-Screen Display 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Row 0 selected Row 1 selected Row 2 selected Row 3 selected Row 4 selected Row 5 selected Row 6 selected Row 7 selected Row 8 selected Row 9 selected Row 10 selected Row 11 selected Invalid selection Others 4-8 S3C880A/F880A CONTROL REGISTERS CLKCON -- System Clock Control Register Bit Identifier nRESET Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W D4H .2 0 R/W .1 0 R/W Set 1 .0 0 R/W Register addressing mode only Oscillator IRQ Wake-up Function Enable Bit 0 1 Enable IRQ for main system oscillator wake-up in power-down mode Disable IRQ for main system oscillator wake-up in power-down mode .6 and .5 Main Oscillator Stop Control Bits 0 0 1 1 0 1 0 1 No effect No effect Stop main oscillator No effect .4 and .3 CPU Clock (System Clock) Selection Bits (1) 0 0 1 1 0 1 0 1 Divide by 16 (fOSC/16) Divide by 8 (fOSC/8) Divide by 2 (fOSC/2) Non-divided clock (fOSC) .2-.0 Subsystem Clock Selection Bits (2) 1 0 Others 1 Invalid selection for S3C880A/F880A Select main system clock (MCLK) NOTES: 1. After a reset, the slowest clock (divide by 16) is selected as the system clock. To select faster clock speeds, load the appropriate values to CLKCON.3 and CLKCON.4. 2. These selection bits are required only for systems that have a main clock and a subsystem clock. The S3C880A/F880A microcontrollers have only a main oscillator (and an L-C oscillator for the OSD module). For this reason, the setting '101B' is invalid. 4-9 CONTROL REGISTERS S3C880A/F880A CLMCON -- OSD Column Control Register Bit Identifier nRESET Value Read/Write Addressing Mode .7-.3 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W F3H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only Left Margin Display Position Control Bits (16 + 4 x LMG value of 0-31 dots) 0 0 0 0 0 0 *** 1 1 1 1 1 0 0 0 1 Left margin = 16 dot clocks Left margin = 16 + 4 x 1 dot clock *** Left margin = 16 + 4 x 31 dot clocks .2-.0 Inter-Column Spacing Control Selection (0-7 dots) 0 0 0 0 *** 1 1 1 0 1 No inter-column spacing Inter-column spacing = 1 dot *** Inter-column spacing = 7 dots NOTE: To set left margin and inter-column spacing, separate decimal values must be calculated, converted to their binary equivalents, and then written to the CLMCON register. 4-10 S3C880A/F880A CONTROL REGISTERS COLBUF -- OSD Character Color Buffer Bit Identifier nRESET Value Read/Write Addressing Mode .7 - - .6 - - .5 - - .4 x R/W .3 x R/W FCH .2 x R/W Set 1, Bank 1 .1 x R/W .0 x R/W Register addressing mode only .7-.6 Not used for the S3C880A/F880A. .5 Video RAM Bit-9 Enable Bit 0 1 Disable VRAM bit-9 Enable VAM bit-9 .4 Video RAM Bit-8 Enable Bit 0 1 Disable VRAM bit-8 Enable VRAM bit-8 .3 H/T and BGRND Enable Bit 0 1 Disable H/T and BRGND Enable H/T and BRGND .2-.0 Character Color Selection Bits .2 0 0 0 0 1 1 1 1 .1 0 0 1 1 0 0 1 1 .0 0 1 0 1 0 1 0 1 OSDCOL.0 = 0 Black Blue Green Cyan Red Magenta Yellow White OSDCOL.0 = 1 Color mode 0 Color mode 1 Color mode 2 Color mode 3 Color mode 4 Color mode 5 Color mode 6 Color mode 7 4-11 CONTROL REGISTERS S3C880A/F880A COLCON -- OSD Background Color Control Register Bit Identifier nRESET Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W F4H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only Frame Background Color Enable Bit 0 1 Disable frame background color (no background color is displayed) Enable frame background color .6-.4 Frame Background Color Selection Bits (when .7 = "1") .6 0 0 0 0 1 1 1 1 .5 0 0 1 1 0 0 1 1 .4 0 1 0 1 0 1 0 1 OSDCOL.0 = 0 Black Blue Green Cyan Red Magenta Yellow White OSDCOL.0 = 1 Color mode 0 Color mode 1 Color mode 2 Color mode 3 Color mode 4 Color mode 5 Color mode 6 Color mode 7 .3 Character Background Color Enable Bit 0 1 Disable character background color (no background color is displayed) Enable character background color display .2-.0 Character Background Color Selection Bits (when .3 = "1") .2 0 0 0 0 1 1 1 1 .1 0 0 1 1 0 0 1 1 .0 0 1 0 1 0 1 0 1 OSDCOL.0 = 0 Black Blue Green Cyan Red Magenta Yellow White OSDCOL.0 = 1 Color mode 0 Color mode 1 Color mode 2 Color mode 3 Color mode 4 Color mode 5 Color mode 6 Color mode 7 4-12 S3C880A/F880A CONTROL REGISTERS DSPCON -- On-Screen Display Control Register Bit Identifier nRESET Value Read/Write Addressing Mode .7-.4 .7 0 R .6 0 R .5 0 R .4 0 R .3 0 R/W F5H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only OSD Row Counter (Read-only) 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Row 0 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 Row 9 Row 10 Row 11 1100-1111 are not used Others .3 Clock Edge Selection for H/V-Sync Polarity 0 1 Rising edge Falling edge .2-.1 Halftone or Background Color Selection Bits 0 0 1 1 0 1 0 1 Character background color Not used Halftone output Character halftone and background color .0 Display Enable Bit 0 1 Disable OSD (turn off L-C OSC) Enable OSD (turn on L-C OSC) 4-13 CONTROL REGISTERS S3C880A/F880A EMT -- External Memory Timing Register Bit Identifier nRESET Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W FEH .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 - - Register addressing mode only External nWAIT Input Function Enable Bit 0 1 Disable nWAIT input function for external device (normal operating mode) Enable nWAIT input function for external device .6 Slow Memory Timing Enable Bit 0 1 Disable slow memory timing Enable slow memory timing .5 and .4 Program Memory Automatic Wait Control Bits 0 0 1 1 0 1 0 1 No wait (normal operation) Wait one cycle Wait two cycles Wait three cycles .3 and .2 Data Memory Automatic Wait Control Bits 0 0 1 1 0 1 0 1 No wait (normal operation) Wait one cycle Wait two cycles Wait three cycles .1 Stack Area Selection Bit 0 1 Select internal register file area Select external data memory area .0 NOTE: Not used for the S3C880A/F880A. Because an external interface is not implemented for the S3C880A/F880A, the EMT values should always be "0". 4-14 S3C880A/F880A CONTROL REGISTERS FADECON -- OSD Fade Control Register Bit Identifier nRESET Value Read/Write Addressing Mode .7 - - .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W F1H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only .7 Not used for the S3C880A/F880A. .6 Fade Function Enable Bit 0 1 Fade disable Fade enable .5 Fade Direction Selection Bit 0 1 Fade before matrix Fade after matrix .4-.0 Halftone or Background Color Selection Bits (1) 0 0 0 0 0 0 0 0 0 1 Line 0 Line 1 .... 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 Line 16 Line 17 Inter-row space Line 1 (1H) Inter-row space Line 2 (1H) Inter-row space Line 3 (1H) Inter-row space Line 4 (1H) Inter-row space Line 5 (1H) Inter-row space Line 6 (1H) Inter-row space Line 7 (1H) Not used .... .... 1 NOTE: .... 1 1 Not used 1 1 There are two choices of fade direction: before (FADECON.5="0") and after (FADECON.5="1"). When you select fade before, the character matrix is faded starting with current line +1 (not including current line). When you select fade after, the character matrix is faded starting with current line. 4-15 CONTROL REGISTERS S3C880A/F880A FLAGS -- System Flags Register Bit Identifier nRESET Value Read/Write Addressing Mode .7 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W D5H .2 x R/W .1 0 R/W Set 1 .0 0 R/W Register addressing mode only Carry Flag (C) 0 1 Operation does not generate a carry or borrow condition Operation generates a carry-out or borrow into high-order bit-7 .6 Zero Flag (Z) 0 1 Operation result is a non-zero value Operation result is zero .5 Sign Flag (S) 0 1 Operation generates a positive number (MSB = "0") Operation generates a negative number (MSB = "1") .4 Overflow Flag (V) 0 1 Operation result is + 127 or - 128 Operation result is > + 127 or < - 128 .3 Decimal Adjust Flag (D) 0 1 Add operation has completed Subtraction operation has completed .2 Half-Carry Flag (H) 0 1 No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3 .1 Fast Interrupt Status Flag (FIS) 0 1 Cleared automatically during an interrupt return (IRET) Automatically set to logic one during a fast interrupt service routine .0 Bank Address Selection Flag (BA) 0 1 Bank 0 is selected (using the SB0 instruction) Bank 1 is selected (using the SB1 instruction) 4-16 S3C880A/F880A CONTROL REGISTERS HTCON -- Halftone Signal Control Register Bit Identifier nRESET Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W F6H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only Halftone Output Polarity Selection Bit (HT Only) 0 Active high (normal halftone output is Low level) 1 Active low (normal halftone output is High level) RGB Output Polarity Selection Bit 0 Active high (normal RGB polarity is Low level) 1 Active low (normal RGB polarity is High level) OSD ROW Interrupt Enable Bit 0 Disable the OSD ROW interrupt 1 Enable the OSD ROW interrupt OSD ROW Interrupt Pending Bit 0 No interrupt is pending (when read); clear pending bit (when write) 1 Interrupt is pending (when read); no effect (when write) Halftone Function Enable Bit 0 Disable the halftone control signal 1 Enable the halftone control signal Halftone Option Selection Bit 0 Halftone output for character periods only (as selected by video RAM bit-13) 1 Halftone output for all frame periods (regardless of video RAM bit-13 setting) V-Sync Interrupt Enable Bit 0 Disable the V-sync interrupt 1 Enable the V-sync interrupt V-Sync Interrupt Pending Bit 0 No OSD ROW interrupt is pending (when read) 0 Clear pending bit (when write) 1 OSD ROW interrupt is pending (when read) 1 No effect (when write) .6 .5 .4 .3 .2 .1 .0 4-17 CONTROL REGISTERS S3C880A/F880A IMR -- Interrupt Mask Register Bit Identifier nRESET Value Read/Write Addressing Mode .7 .7 x R/W .6 x R/W .5 - - .4 x R/W .3 x R/W DDH .2 x R/W .1 x R/W Set 1 .0 x R/W Register addressing mode only Interrupt Priority Level 7 (IRQ7) Enable Bit; V-Sync 0 1 Disable IRQ7 interrupt Enable IRQ7 interrupt .6 Interrupt Priority Level 6 (IRQ6) Enable Bit; Timer A 0 1 Disable IRQ6 interrupt Enable IRQ6 interrupt .5 Not used for S3C880A/F880A .4 Interrupt Priority Level 4 (IRQ4) Enable Bit; P1.2 and P1.3 External Interrupt 0 1 Disable IRQ4 interrupt Enable IRQ4 interrupt .3 Interrupt Priority Level 3 (IRQ3) Enable Bit; CAPA 0 1 Disable IRQ3 interrupt Enable IRQ3 interrupt .2 Interrupt Priority Level 2 (IRQ2) Enable Bit; OSD ROW Interrupt 0 1 Disable IRQ2 interrupt Enable IRQ2 interrupt .1 Interrupt Priority Level 1 (IRQ1) Enable Bit; P1.0 and P1.1 External Interrupt 0 1 Disable IRQ1 interrupt Enable IRQ1 interrupt .0 Interrupt Priority Level 0 (IRQ0) Enable Bit; T0INT (Match) 0 1 Disable IRQ0 interrupt Enable IRQ0 interrupt 4-18 S3C880A/F880A CONTROL REGISTERS IPH -- Instruction Pointer (High Byte) Bit Identifier nRESET Value Read/Write Addressing Mode .7-.0 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W DAH .2 x R/W .1 x R/W Set 1 .0 x R/W Register addressing mode only Instruction Pointer Address (High Byte) The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15-IP8). The lower byte of the IP address is located in the IPL register (DBH). IPL -- Instruction Pointer (Low Byte) Bit Identifier nRESET Value Read/Write Addressing Mode .7 - .0 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W DBH .2 x R/W .1 x R/W Set 1 .0 x R/W Register addressing mode only Instruction Pointer Address (Low Byte) The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (IP7-IP0). The upper byte of the IP address is located in the IPH register (DAH). 4-19 CONTROL REGISTERS S3C880A/F880A IPR -- Interrupt Priority Register Bit Identifier nRESET Value Read/Write Addressing Mode .7, .4, and .1 .7 x R/W .6 x R/W .5 - - .4 x R/W .3 x R/W FFH .2 x R/W Set 1, Bank 0 .1 x R/W .0 x R/W Register addressing mode only Priority Control Bits for Interrupt Groups A, B, and C (1) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Group priority undefined B>C>A A>B>C B>A>C C>A>B C>B>A A>C>B Group priority undefined .6 Interrupt Group C Priority Control Bit 0 1 IRQ6 > IRQ7 IRQ7 > IRQ6 .5 Not used for the S3C880A/F880A (2) .3 Interrupt Sub Group B Priority Control Bit 0 1 IRQ3 > IRQ4 IRQ4 > IRQ3 .2 Interrupt Group B Priority Control Bit 0 1 IRQ2 > (IRQ3, IRQ4) (IRQ3, IRQ4) > IRQ2 .0 Interrupt Group A Priority Control Bit 0 1 IRQ0 > IRQ1 IRQ1 > IRQ0 NOTES: 1. Interrupt group A is IRQ0 and IRQ1; interrupt group B is IRQ2, IRQ3, and IRQ4; interrupt group C is IRQ6 and IRQ7. 2. Interrupt level IRQ5 is not used in the S3C880A/F880A interrupt structure. For this reason, IPR.5 is not used. 4-20 S3C880A/F880A CONTROL REGISTERS IRQ -- Interrupt Request Register Bit Identifier nRESET Value Read/Write Addressing Mode .7 .7 0 R .6 0 R .5 - - .4 0 R .3 0 R DCH .2 0 R .1 0 R Set 1 .0 0 R Register addressing mode only Interrupt Level 7 (IRQ7) Request Pending Bit; V-Sync 0 1 No IRQ7 interrupt pending IRQ7 interrupt is pending .6 Interrupt Level 6 (IRQ6) Request Pending Bit; Timer A 0 1 No IRQ6 interrupt pending IRQ6 interrupt is pending .5 .4 Not used for the S3C880A/F880A Interrupt Level 4 (IRQ4) Request Pending Bit; P1.2 and P1.3 External Interrupt 0 1 No IRQ4 interrupt pending IRQ4 interrupt is pending .3 Interrupt Level 3 (IRQ3) Request Pending Bit; CAPA 0 1 No IRQ3 interrupt pending IRQ3 interrupt is pending .2 Interrupt Level 2 (IRQ2) Request Pending Bit; OSD ROW Interrupt 0 1 No IRQ2 interrupt pending IRQ2 interrupt is pending .1 Interrupt Level 1 (IRQ1) Request Pending Bit; P1.0 and P1.1 External Interrupt 0 1 No IRQ1 interrupt pending IRQ1 interrupt is pending .0 Interrupt Level 0 (IRQ0) Request Pending Bit; T0INT (Match) 0 1 No IRQ0 interrupt pending IRQ0 interrupt is pending NOTE: Interrupt level request pending bits can be polled by software to detect an interrupt request pending condition on any of the seven valid interrupt levels (IRQ0-IRQ4, IRQ6, and IRQ7). Interrupt pending bits are read-only addressable. 4-21 CONTROL REGISTERS S3C880A/F880A OSDCOL -- OSD Space Color Control Register Bit Identifier nRESET Value Read/Write Addressing Mode .7 - - .6 - - .5 - - .4 0 R/W .3 0 R/W E4H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only .7-,5 Not used for the S3C880A/F880A. Inter Character Smoothing Control Bit (note) 0 1 Disable inter character smoothing Enable inter character smoothing .4 .3 Fringe Dot Size Selection Bit 0 1 1 dot 1/2 dot .2 Inter-row Space Half Tone 0 1 Depend on character background half tone Depend on frame background half tone .1 Inter-row Space Color 0 1 Depend on character background color Depend on frame background color .0 RGB Output Selection Bit 0 1 Digital RGB output (disable palette color mode) Analog RGB output (enable palette color mode) NOTE: In 1-dot fringe mode (OSDCOL.3 = "0") , Inter-character smooth function is disabled. 4-22 S3C880A/F880A CONTROL REGISTERS OSDFLD -- OSD Field Control Register Bit Identifier nRESET Value Read/Write Addressing Mode .7-,6 .5 .7 - - .6 - - .5 x R .4 0 R/W .3 0 R/W E5H .2 1 R/W Set 1, Bank 1 .1 1 R/W .0 0 R/W Register addressing mode only Not used for the S3C880A/F880A. Field Data (Read Only) 0 1 Even field Odd field .4 H-sync Detect Position Select Bit 0 1 Detect H-sync before V-sync Detect H-sync after V-sync .3-.0 Even Field Range 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Not used fCPU/16 x 1 fCPU /16 x 2 fCPU /16 x 3 fCPU /16 x 4 fCPU /16 x 5 fCPU /16 x 6 (Reset value) fCPU /16 x 7 fCPU /16 x 8 fCPU /16 x 9 fCPU /16 x 10 fCPU /16 x 11 fCPU /16 x 12 fCPU /16 x 13 fCPU /16 x 14 fCPU /16 x 15 4-23 CONTROL REGISTERS S3C880A/F880A OSDFRG1 -- OSD Fringe/Border Control Register 1 Bit Identifier nRESET Value Read/Write Addressing Mode .7-.0 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E0H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only Fringe/Border Function Enable Bit 0 1 Disable Fringe/Border function at row n (n = 0-7) Enable Fringe/Border function at row n (n = 0-7) NOTE: Row n is respectively correspond with bit n (n = 0-7). 4-24 S3C880A/F880A CONTROL REGISTERS OSDFRG2 -- OSD Fringe/Border Control Register 2 Bit Identifier nRESET Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E1H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only Fringe or Border Selection Bit 0 1 Border function select Fringe function select .6-.4 Fringe/Border Color Selection Bits (.6: Red, .5: Green, .4: Blue) .6 0 0 0 0 1 1 1 1 .5 0 0 1 1 0 0 1 1 .4 0 1 0 1 0 1 0 1 OSDCOL.0 = 0 Black Blue Green Cyan Red Magenta Yellow White OSDCOL.0 = 1 Color mode 0 Color mode 1 Color mode 2 Color mode 3 Color mode 4 Color mode 5 Color mode 6 Color mode 7 .3-.0 Fringe/Border Function Enable Bits 0 1 Disable Fringe/Border function at row n (n = 8-11) Enable Fringe/Border function at row n (n = 8-11) NOTE: Row 8, row 9, row 10, row 11 are correspond with bit 0, bit 1, bit 2, bit3, respectively. 4-25 CONTROL REGISTERS S3C880A/F880A OSDPLTB1 -- OSD Palette Color Mode Register B1 Bit Identifier nRESET Value Read/Write Addressing Mode .7-.6 .7 1 R/W .6 1 R/W .5 0 R/W .4 0 R/W .3 1 R/W EAH .2 1 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only OSD Mode 3 Blue Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .5-.4 OSD Mode 2 Blue Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .3-.2 OSD Mode 1 Blue Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .1-.0 OSD Mode 1 Blue Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % 4-26 S3C880A/F880A CONTROL REGISTERS OSDPLTB2 -- OSD Palette Color Mode Register B2 Bit Identifier nRESET Value Read/Write Addressing Mode .7-.6 .7 1 R/W .6 1 R/W .5 0 R/W .4 0 R/W .3 1 R/W EBH .2 1 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only OSD Mode 7 Blue Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .5-.4 OSD Mode 6 Blue Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .3-.2 OSD Mode 5 Blue Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .1-.0 OSD Mode 4 Blue Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % 4-27 CONTROL REGISTERS S3C880A/F880A OSDPLTG1 -- OSD Palette Color Mode Register G1 Bit Identifier nRESET Value Read/Write Addressing Mode .7-.6 .7 1 R/W .6 1 R/W .5 1 R/W .4 1 R/W .3 0 R/W E8H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only OSD Mode 3 Green Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .5-.4 OSD Mode 2 Green Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .3-.2 OSD Mode 1 Green Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .1-.0 OSD Mode 1 Green Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % 4-28 S3C880A/F880A CONTROL REGISTERS OSDPLTG2 -- OSD Palette Color Mode Register G2 Bit Identifier nRESET Value Read/Write Addressing Mode .7-.6 .7 1 R/W .6 1 R/W .5 1 R/W .4 1 R/W .3 0 R/W E9H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only OSD Mode 7 Green Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .5-.4 OSD Mode 6 Green Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .3-.2 OSD Mode 5 Green Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .1-.0 OSD Mode 4 Green Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % 4-29 CONTROL REGISTERS S3C880A/F880A OSDPLTR1 -- OSD Palette Color Mode Register R1 Bit Identifier nRESET Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E6H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only OSD Mode 3 Red Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .5-.4 OSD Mode 2 Red Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .3-.2 OSD Mode 1 Red Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .1-.0 OSD Mode 1 Red Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % 4-30 S3C880A/F880A CONTROL REGISTERS OSDPLTR2 -- OSD Palette Color Mode Register R2 Bit Identifier nRESET Value Read/Write Addressing Mode .7-.6 .7 1 R/W .6 1 R/W .5 1 R/W .4 1 R/W .3 1 R/W E7H .2 1 R/W Set 1, Bank 1 .1 1 R/W .0 1 R/W Register addressing mode only OSD Mode 7 Red Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .5-.4 OSD Mode 6 Red Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .3-.2 OSD Mode 5 Red Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % .1-.0 OSD Mode 4 Red Level 0 0 1 1 0 1 0 1 Disable 33 % 66 % 100 % 4-31 CONTROL REGISTERS S3C880A/F880A OSDSMH1 -- OSD Smooth Control Register 1 Bit Identifier nRESET Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E2H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only Row 7 Smooth Function Enable Bit 0 1 Disable smooth function at Row 7 Enable smooth function at Row 7 .6 Row 6 Smooth Function Enable Bit 0 1 Disable smooth function at Row 6 Enable smooth function at Row 6 .5 Row 5 Smooth Function Enable Bit 0 1 Disable smooth function at Row 5 Enable smooth function at Row 5 .4 Row 4 Smooth Function Enable Bit 0 1 Disable smooth function at Row 4 Enable smooth function at Row 4 .3 Row 3 Smooth Function Enable Bit 0 1 Disable smooth function at Row 3 Enable smooth function at Row 3 .2 Row 2 Smooth Function Enable Bit 0 1 Disable smooth function at Row 2 Enable smooth function at Row 2 .1 Row 1 Smooth Function Enable Bit 0 1 Disable smooth function at Row 1 Enable smooth function at Row 1 .0 Row 0 Smooth Function Enable Bit 0 1 Disable smooth function at Row 0 Enable smooth function at Row 0 4-32 S3C880A/F880A CONTROL REGISTERS OSDSMH2 -- OSD Smooth Control Register 2 Bit Identifier nRESET Value Read/Write Addressing Mode .7 - - .6 - - .5 - - .4 - - .3 0 R/W E3H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only .7-,4 Not used for the S3C880A/F880A .3 Row 11 Smooth Function Enable Bit 0 1 Disable smooth function at Row 11 Enable smooth function at Row 11 .2 Row 10 Smooth Function Enable Bit 0 1 Disable smooth function at Row 10 Enable smooth function at Row 10 .1 Row 9 Smooth Function Enable Bit 0 1 Disable smooth function at Row 9 Enable smooth function at Row 9 .0 Row 8 Smooth Function Enable Bit 0 1 Disable smooth function at Row 8 Enable smooth function at Row 8 4-33 CONTROL REGISTERS S3C880A/F880A P0CONH -- Port 0 Control Register (High Byte) Bit Identifier nRESET Value Read/Write Addressing Mode .7 and .6 .7 1 R/W .6 1 R/W .5 1 R/W .4 1 R/W .3 0 R/W E4H .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only Port 0.7 Configuration Bits 0 0 1 1 0 1 0 1 Input mode ADC Input mode Open-drain output mode Open-drain output mode .5 and .4 Port 0.6 Configuration Bits 0 0 1 1 0 1 0 1 Input mode ADC Input mode Open-drain output mode Open-drain output mode .3 and .2 Port 0.5 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode Push-pull output mode Push-pull output mode .1 and .0 Port 0.4 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode Push-pull output mode Push-pull output mode 4-34 S3C880A/F880A CONTROL REGISTERS P0CONL -- Port 0 Control Register (Low Byte) Bit Identifier nRESET Value Read/Write Addressing Mode .7 and .6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E5H .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only Port 0.3 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode N-channel open-drain output mode (5 V load) Push-pull output mode .5 and .4 Port 0.2 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode N-channel open-drain output mode (5 V load) Push-pull output mode .3 and .2 Port 0.1 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode N-channel open-drain output mode (5 V load) Push-pull output mode .1 and .0 Port 0.0 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode N-channel open-drain output mode (5 V load) Push-pull output mode 4-35 CONTROL REGISTERS S3C880A/F880A P1CONH -- Port 1 Control Register (High Byte) Bit Identifier nRESET Value Read/Write Addressing Mode .7 and .6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 1 R/W E6H .2 1 R/W Set 1, Bank 0 .1 1 R/W .0 1 R/W Register addressing mode only Port 1.7/T0CK Configuration Bits 0 0 1 1 0 1 0 1 Input mode Timer 0 clock Input mode Push-pull output mode Push-pull output mode .5 and .4 Port 1.6 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode Push-pull output mode Push-pull output mode .3 and .2 Port 1.5 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode N-channel open-drain mode (6-volt load capacity) N-channel open-drain mode (6-volt load capacity) .1 and .0 Port 1.4 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode N-channel open-drain mode (6-volt load capacity) N-channel open-drain mode (6-volt load capacity) 4-36 S3C880A/F880A CONTROL REGISTERS P1CONL -- Port 1 Control Register (Low Byte) Bit Identifier nRESET Value Read/Write Addressing Mode .7 and .6 .7 1 R/W .6 1 R/W .5 1 R/W .4 1 R/W .3 1 R/W E7H .2 1 R/W Set 1, Bank 0 .1 1 R/W .0 1 R/W Register addressing mode only Port 1.3/INT3 Configuration Bits 0 0 1 1 0 1 0 1 Input mode; interrupt disabled Input mode; interrupt on rising edge Input mode; interrupt on falling edge N-channel open-drain output mode (6-volt load capacity) .5 and .4 Port 1.2/INT2 Configuration Bits 0 0 1 1 0 1 0 1 Input mode; interrupt disabled Input mode; interrupt on rising edge Input mode; interrupt on falling edge N-channel open-drain output mode (6-volt load capacity) .3 and .2 Port 1.1/INT1 Configuration Bits 0 0 1 1 0 1 0 1 Input mode; interrupt disabled Input mode; interrupt on rising edge Input mode; interrupt on falling edge N-channel open-drain output mode (6-volt load capacity) .1 and .0 Port 1.0/INT0 Configuration Bits 0 0 1 1 0 1 0 1 Input mode; interrupt disabled Input mode; interrupt on rising edge Input mode; interrupt on falling edge N-channel open-drain output mode (6-volt load capacity) 4-37 CONTROL REGISTERS S3C880A/F880A P2CONH -- Port 2 Control Register (High Byte) Bit Identifier nRESET Value Read/Write Addressing Mode .7 and .6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E8H .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only Port 2.7/OSDHT Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode (5-volt load capacity) Push-pull output mode OSD half-tone output mode (push-pull circuit type) .5 and .4 Port 2.6/T0 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode (5-volt load capacity) Push-pull output mode Timer 0 output mode (interval or PWM; N-channel open-drain type) .3 and .2 Port 2.5/PWM0 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode (5-volt load capacity) Push-pull output mode PWM0 output mode (push-pull circuit type) .1 and .0 Port 2.4/PWM4 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode (5-volt load capacity) Push-pull output mode PWM4 output mode (N-channel open-drain type) 4-38 S3C880A/F880A CONTROL REGISTERS P2CONL -- Port 2 Control Register (Low Byte) Bit Identifier nRESET Value Read/Write Addressing Mode .7 and .6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E9H .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only Port 2.3/PWM3 Configuration Bits 0 0 1 1 0 1 0 1 Normal input mode Normal input mode PWM3 output mode; N-channel, open-drain output mode With 5-volt load capacity Push-pull output mode .5 and .4 Port 2.2/PWM2 Configuration Bits 0 0 1 1 0 1 0 1 Normal input mode Normal input mode PWM2 output mode; N-channel, open-drain output mode With 5-volt load capacity Push-pull output mode .3 and .2 Port 2.1/PWM1 Configuration Bits 0 0 1 1 0 1 0 1 Normal input mode Normal input mode PWM1 output mode; N-channel, open-drain output mode With 5-volt load capacity Push-pull output mode .1 and .0 Port 2.0/PWM5 Configuration Bits 0 0 1 1 0 1 0 1 Normal input mode Normal input mode PWM5 output mode; N-channel, open-drain output mode With 5-volt load capacity Push-pull output mode 4-39 CONTROL REGISTERS S3C880A/F880A P3CONL -- Port 3 Control Register (Low Byte) Bit Identifier nRESET Value Read/Write Addressing Mode .7 - - .6 - - .5 - - .4 - - .3 1 R/W EBH .2 1 R/W Set 1, Bank 0 .1 1 R/W .0 1 R/W Register addressing mode only .7 - .4 No effect .3 and .2 Port 3.1/ADC1 Configuration Bits 0 0 1 1 0 1 0 1 Input mode ADC input mode Input mode N-channel, open-drain output mode with 5-volt load capacity .1 and .0 Port 3.0/ADC0 Configuration Bits 0 0 1 1 0 1 0 1 Input mode ADC input mode Input mode N-channel, open-drain output mode with 5-volt load capacity 4-40 S3C880A/F880A CONTROL REGISTERS PP -- Register Page Pointer Bit Identifier nRESET Value Read/Write Addressing Mode .7-.4 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W DFH .2 0 R/W .1 0 R/W Set 1 .0 0 R/W Register addressing mode only Destination Register Page Selection Bits 0 0 0 0 0 0 0 0 *** 0 0 1 1 0 1 0 1 Destination: page 0 Destination: page 1 Destination: page 2 Not used for the S3C880A/F880A " 1 1 1 1 Not used for the S3C880A/F880A .3-.0 Source Register Page Selection Bits 0 0 0 0 0 0 0 0 *** 0 0 1 1 0 1 0 1 Source: page 0 Source: page 1 Source: page 2 Not used for the S3C880A/F880A " 1 1 1 1 Not used for the S3C880A/F880A 4-41 CONTROL REGISTERS S3C880A/F880A PWMCON -- PWM Control Register Bit Identifier nRESET Value Read/Write Addressing Mode .4, .7, and .6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W F8H .2 - - Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only 3-Bit Prescaler Value for PWM Counter Input Clock 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Non-divided input clock Divided-by-two input clock Divided-by-three input clock Divided-by-four input clock Divided-by-five input clock Divided-by-six input clock Divided-by-seven input clock Divided-by-eight input clock .5 PWM Counter Enable Bit 0 1 Stop PWM counter operation Start (or resume) PWM counter operation .3 Capture A Interrupt Enable Bit 0 1 Disable capture A interrupt Enable capture A interrupt .2 Not used for the S3C880A/F880A .1 and .0 Capture A Module Control Bits 0 0 1 1 0 1 0 1 Disable capture A module Capture on falling edges only Capture on rising edges only Capture on both rising and falling edges 4-42 S3C880A/F880A CONTROL REGISTERS ROWCON -- OSD Row Position Control Register Bit Identifier nRESET Value Read/Write Addressing Mode .7-.3 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W F2H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only Top Margin Display Position Control Value (4 x TMG value of 0-31 dots) 0 0 0 0 0 0 *** 1 1 1 1 1 0 0 0 1 Top margin position = 0H Top margin position = 4H *** Top margin position = 124H .2-.0 Inter-Row Spacing Control Value (0-7H) 0 0 0 0 *** 1 1 1 0 1 No inter-row spacing Inter-row spacing = 1H *** Inter-row spacing = 7H NOTE: To set top margin and inter-row spacing, separate decimal values must be calculated, converted to their binary equivalents, and then written to the ROWCON register. 4-43 CONTROL REGISTERS S3C880A/F880A RP0 -- Register Pointer 0 Bit Identifier nRESET Value Read/Write Addressing Mode .7-.3 .7 1 R/W .6 1 R/W .5 0 R/W .4 0 R/W .3 0 R/W D6H .2 - - .1 - - Set 1 .0 - - Register addressing mode only Register Pointer 0 Address Value Register pointer 0 can independently point to one of the twenty four 8-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset, RP0 points to the address C0H in the register set 1, selecting the 8-byte working register slice C0H-C7H. .2-.0 Not used for the S3C880A/F880A RP1 -- Register Pointer 1 Bit Identifier nRESET Value Read/Write Addressing Mode .7-.3 .7 1 R/W .6 1 R/W .5 0 R/W .4 0 R/W .3 1 R/W D7H .2 - - .1 - - Set 1 .0 - - Register addressing mode only Register Pointer 1 Address Value Register pointer 1 can independently point to one of the twenty four 8-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset, RP1 points to the address C8H in the register set 1, selecting the 8-byte working register slice C8H-CFH. .2-.0 Not used for the S3C880A/F880A. 4-44 S3C880A/F880A CONTROL REGISTERS SPH -- Stack Pointer (High Byte) Bit Identifier nRESET Value Read/Write Addressing Mode .7-.0 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W D8H .2 x R/W .1 x R/W Set 1 .0 x R/W Register addressing mode only Stack Pointer Address (High Byte) The high-byte stack pointer value is the upper 8 bits of the 16-bit stack pointer address (SP15-SP8). The lower byte of the stack pointer value is located in the register SPL (D9H). The SP value is undefined after a reset. SPL -- Stack Pointer (Low Byte) Bit Identifier nRESET Value Read/Write Addressing Mode .7-.0 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W D9H .2 x R/W .1 x R/W Set 1 .0 x R/W Register addressing mode only Stack Pointer Address (Low Byte) The low-byte stack pointer value is the lower 8 bits of the 16-bit stack pointer address (SP7-SP0). The upper byte of the stack pointer value is located in the register SPH (D8H). The SP value is undefined after a reset. 4-45 CONTROL REGISTERS S3C880A/F880A STCON -- Stop Control Register Bit Identifier nRESET Value Read/Write Addressing Mode .7-.0 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W F3H .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only Stop Condition Enable Bits Other set value 10100101 Stop Condition Disable (Stop instruction is not available) Stop Condition Enable (Stop instruction is available) NOTE: When the Stop control register, STCON, is set by '10100101B', Stop instruction is available. The other value except '10100101B' make Stop instruction not available. When Stop condition is disabled, using "stop" instruction make state reset. Once Stop instruction is executed in state of STOP instruction available, the state is changed to Stop instruction not available. 4-46 S3C880A/F880A CONTROL REGISTERS SYM -- System Mode Register Bit Identifier nRESET Value Read/Write Addressing Mode .7 .7 0 R/W .6 - - .5 - - .4 x R/W .3 x R/W DEH .2 x R/W .1 0 R/W Set 1 .0 0 R/W Register addressing mode only Tri-State External Interface Control Bit (1) 0 1 Normal operation (disable tri-state operation) Set external interface lines to high impedance (enable tri-state operation) .6-.5 Not used for the S3C880A/F880A. .4-.2 Fast Interrupt Level Selection Bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Level 0 (IRQ0) Level 1 (IRQ1) Level 2 (IRQ2) Level 3 (IRQ3) Level 4 (IRQ4) Not used for S3C880A/F880A Level 6 (IRQ6) Level 7 (IRQ7) .1 Fast Interrupt Enable Bit 0 1 Disable fast interrupt processing Enable fast interrupt processing .0 Global Interrupt Enable Bit (2) 0 1 Disable global interrupt processing Enable global interrupt processing NOTES: 1. Because the S3C880A/F880A microcontrollers do not have an external interface, bit 7 should always be "0". 2. After a reset, the initialization routine must enable global interrupt processing by executing an EI instruction (and not by writing a "1" to SYM.0). 4-47 CONTROL REGISTERS S3C880A/F880A TACON -- Timer A Control Register Bit Identifier nRESET Value Read/Write Addressing Mode .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W F2H .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 - - Register addressing mode only .7-.4 4-Bit Prescaler for Timer A Clock Input 0 0 0 0 *** 1 1 1 1 0 0 0 1 Divide input by 1 (non-divided) Divide input by 2 *** Divide input by 16 .3 Timer A Clock Source Selection Bit 0 1 CPU clock divided by 1000 Non-divided CPU clock .2 Timer A Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .1 Timer A Interrupt Pending Bit 0 0 1 1 No interrupt pending (when read) Clear pending bit (when write) Interrupt is pending (when read) No effect (when write) .0 Not used for the S3C880A/F880A 4-48 S3C880A/F880A CONTROL REGISTERS T0CON -- Timer 0 Control Register Bit Identifier nRESET Value Read/Write Addressing Mode .7 and .6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W D2H .2 - - .1 0 R/W Set 1 .0 0 R/W Register addressing mode only T0 Input Clock Selection Bits 0 0 1 1 0 1 0 1 fOSC/4096 fOSC/256 fOSC/8 External clock (T0CLK) .5 and .4 T0 Operating Mode Selection Bits 0 0 1 1 0 1 0 1 Interval mode PWM mode PWM mode PWM mode .3 T0 Counter Clear Bit 0 1 No effect Clear the T0 counter (when write) .2 No effect .1 T0 Interrupt Enable Bit 0 1 Disable T0 interrupt Enable T0 interrupt .0 T0 Interrupt Pending Bit 0 0 1 1 No timer 0 interrupt pending (when read) Clear timer 0 pending bit (when write) Timer 0 interrupt is pending (when read) No effect (when write) 4-49 CONTROL REGISTERS S3C880A/F880A VSBCON -- V-SYNC Blank Control Register Bit Identifier nRESET Value Read/Write Addressing Mode .7 - - .6 - - .5 - - .4 0 R/W .3 1 R/W F7H .2 0 R/W .1 0 Set 1, Bank1 .0 1 R/W R/W Register addressing mode only .7 and .5 Not used for the S3C880A/F880A .4-.0 V-SYNC Blank Time Control Bits: 0 0 0 *** 0 0 9 Horizontal Sync 0 0 0 1 1 1 0 0 0 *** 0 1 1 1 0 1 9 Horizontal Sync 10 Horizontal Sync 11 Horizontal Sync *** 1 1 1 1 1 31 Horizontal Sync 4-50 S3C880A/F880A INTERRUPT STRUCTURE 5 OVERVIEW Levels INTERRUPT STRUCTURE The SAM87 interrupt structure has three basic components: levels, vectors, and sources. The CPU recognizes 8 interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more than one vector address, the vector priorities are established in hardware. Each vector can have one or more interrupt sources. Levels provide the highest-level method of interrupt priority assignment and recognition. All peripherals and I/O blocks can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight interrupt levels: IRQ0-IRQ7. Each interrupt level directly corresponds to an interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from device to device. For the S3C880A/F880A microcontrollers, seven levels are recognized: IRQ0-IRQ4, IRQ6, and IRQ7. The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are simply identifiers for the interrupt levels that are recognized by the CPU (IRQ0-IRQ7). The relative priority of different interrupt levels is determined by settings in the interrupt priority register, IPR. Interrupt logic controlled by the IPR settings lets you define additional priority relationship for specific interrupt levels. Vectors Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The maximum number of vectors that can be supported for a given level is 128. (The actual number of vectors used for the S3C8-series microcontrollers is always much smaller.) If an interrupt level has more than one vector address, the vector priorities are set in hardware. The S3C880A/F880A have 9 vectors, one corresponding to each of the 9 possible sources. Sources A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow, for example. Each vector can have several interrupt sources. In the S3C880A/F880A interrupt structure, each source has its own vector address. When a service routine starts, the respective pending bit is either cleared automatically by hardware or "manually" by the program software. The characteristics of the source's pending mechanism determine which method is used to clear its pending bit. INTERRUPT TYPES The three components of the SAM87 interrupt structure described above -- levels, vectors, and sources -- are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3. The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1): Type 1: Type 2: Type 3: One level (IRQn) + one vector (V 1) + one source (S 1) One level (IRQn) + one vector (V 1) + multiple sources (S 1 - Sn) One level (IRQn) + multiple vectors (V 1 - Vn) + multiple sources (S 1 - Sn , Sn+1 - Sn+m) In the S3C880A/F880A interrupt structure, only interrupt types 1 and 3 are implemented. 5-1 INTERRUPT STRUCTURE S3C880A/F880A LEVELS Type 1: IRQn VECTORS V1 SOURCES S1 S1 Type 2: IRQn V1 S2 S3 Sn V1 Type 3: IRQn V2 V3 Vn NOTES: 1. The number of Sn and Vn value is expandable. 2. In the S3F880A implementation, only interrupt types 1 and 3 are used. S1 S2 S3 Sn Sn + 1 Sn + 2 Sn + m Figure 5-1. S3C8-Series Interrupt Types S3C880A/F880A INTERRUPT STRUCTURE The S3C880A/F880A microcontrollers have 9 standard interrupt sources. Nine different vector addresses are used to support these interrupt sources. Seven of the eight available levels are used for the interrupt structure: IRQ0-IRQ4, IRQ6, and IRQ7. The device-specific interrupt structure is shown in Figure 5-2. When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first. (The relative priorities of multiple interrupts within a single level are hardwired.) When an interrupt request is granted, interrupt processing starts: subsequent interrupts are disabled and the program counter value and status flags are pushed to stack. The starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed. 5-2 S3C880A/F880A INTERRUPT STRUCTURE LEVELS IRQ0 IRQ1 VECTORS FCH C0H C2H 0 1 SOURCES Timer 0 interrupt (match) P1.0 external interrupt P1.1 external interrupt OSD ROW interrupt Capture A (8-bit) 0 1 P1.2 external interrupt P1.3 external interrupt Timer A V-sync IDENTIFIER T0INT P10INT P11INT ROWINT CAPA P12INT P13INT TAINT VSYNC RESET S/W H/W H/W S/W H/W H/W H/W S/W S/W IRQ2 IRQ3 IRQ4 C4H 02H C6H C8H IRQ6 IRQ7 BEH D4H NOTES: 1. The interrupt level IRQ5 is not used in the S3F880A interrupt structure. 2. For interrupt levels with two or more vectors, the lowest vector address usually has the highest priority. For example, C0H has higher priority (0) than C2H (1) within the level IRQ1. These priorities (see numbers) are hardwired. 3. The interrupt names in the 'Identifier' column are used in this documentation to refer to specific interrupts, as distinguished from the interrupt source name or the pin at which an external interrupt request arrives. Figure 5-2. S3C880A/F880A Interrupt Structure 5-3 INTERRUPT STRUCTURE S3C880A/F880A INTERRUPT VECTOR ADDRESSES Interrupt vector addresses for the S3C880A/F880A are stored in the first 256 bytes of the ROM. The reset address is 0100H. Vectors for all interrupt levels are stored in the vector address area (0H-FFH). Unused ROM in the range 00H-FFH can be used as program memory locations. You must be careful, however, not to overwrite interrupt vector addresses stored in this area. (Decimal) 45,151 (HEX) BFFFH (for S3F880A) Addressable Program Memory (ROM) Area 256 255 Interrupt Vector Address Area 0 100H FFH nRESET Address Figure 5-3. ROM Vector Address Area 5-4 S3C880A/F880A INTERRUPT STRUCTURE Table 5-1. S3C880A/F880A Interrupt Vectors Vector Address Decimal Value 252 212 200 198 196 194 192 190 2 Hex Value FCH D4H C8H C6H C4H C2H C0H BEH 02H Timer 0 (match) V-sync P1.3 external interrupt P1.2 external interrupt OSD ROW interrupt P1.1 external interrupt P1.0 external interrupt Timer A Capture A (8-bit) IRQ6 IRQ3 IRQ2 IRQ1 Interrupt Source Request Interrupt Level IRQ0 IRQ7 IRQ4 Priority in Level - - 1 0 - 1 0 - - Reset/Clear H/W S/W NOTES: 1. Interrupt priorities are identified in inverse order: '0' is the highest priority, '1' is the next highest, and so on. 2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority over one with a higher vector address. (The priorities within a level are hardwired) For example, in the interrupt level IRQ1, the higher-priority interrupt vector is the P1.0 external interrupt, vector C0H; the lower-priority interrupt within that level is the P1.1 external interrupt, vector C2H. 5-5 INTERRUPT STRUCTURE S3C880A/F880A ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) The Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are serviced as they occur, and according to established priorities. The system initialization routine that is executed following a reset must always contain an EI instruction (assuming one or more interrupts are used in the application). During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register. Although you can manipulate SYM.0 directly to enable or disable interrupts, we recommend that you use the EI and DI instructions instead. SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources, four system-level control registers control interrupt processing: -- Each interrupt level is enabled or disabled (masked) by bit settings in the interrupt mask register (IMR). -- Relative priorities of interrupt levels are controlled by the interrupt priority register (IPR). -- The interrupt request register (IRQ) contains interrupt pending flags for each level. -- The system mode register (SYM) dynamically enables or disables global interrupt processing. SYM settings also enable fast interrupts and control external interface, if implemented. Table 5-2. Interrupt Control Register Overview Control Register System mode register Interrupt mask register ID SYM IMR R/W R/W R/W Function Description Global interrupt processing enable and disable, fast interrupt processing. Bit settings in the IMR register enable and disable interrupt processing for each of the seven recognized interrupt levels, IRQ0-IRQ4, IRQ6, and IRQ7. Controls the relative processing priorities of the interrupt levels. For the S3C880A/F880A, the seven levels are organized into three groups: A, B, and C. Group A includes IRQ0 and IRQ1, group B is IRQ2, IRQ3, and IRQ4, and group C is IRQ6 and IRQ7. This register contains a request pending bit for each interrupt level. Interrupt priority register IPR R/W Interrupt request register IRQ R 5-6 S3C880A/F880A INTERRUPT STRUCTURE INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: either globally, or by specific interrupt level and source. The system-level control points in the interrupt structure are therefore: -- Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 ) -- Interrupt level enable and disable settings (IMR register) -- Interrupt level priority settings (IPR register) -- Interrupt source enable and disable settings in the corresponding peripheral control register(s) NOTE When writing an interrupt service routine, be sure that it properly manages the register pointer values (RP0 and RP1). "EI" Instruction Execution RESET S R Q Interrupt Pending Register Polling Cycle Source Interrupt Source Interrupts Enable Interrupt Request Register (Read-only) Interrupt Priority Register Vector Interrupt Cycle Interrupt Mask Register NOTE: In the S3F880A microcontrollers, only seven interrupt levels (IRQ0-IRQ4, IRQ6, and IRQ7) are recognized by the CPU. Global Interrupt Control (EI, DI or SYM.0 manipulation) Figure 5-4. Interrupt Function Diagram 5-7 INTERRUPT STRUCTURE S3C880A/F880A PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is a corresponding peripheral control register (or registers) that controls the interrupts generated by the peripheral. These registers and their locations are listed in Table 5-3. Table 5-3. Interrupt Source Control Registers Interrupt Source Timer 0 (match) P1.0 external interrupt P1.1 external interrupt OSD ROW interrupt Capture A (8-bit) P1.2 external interrupt P1.3 external interrupt Timer A V-sync IRQ6 IRQ7 TACON HTCON Set 1, bank 0, F2H Set 1, bank 1, F6H IRQ2 IRQ3 IRQ4 HTCON PWMCON P1CONL Set 1, bank 1, E6H Set 1, bank 0, F8H Set 1, bank 0, E7H Interrupt Level IRQ0 IRQ1 Control Register T0CON P1CONL Register Location Set 1, D2H Set 1, bank 0, E7H 5-8 S3C880A/F880A INTERRUPT STRUCTURE SYSTEM MODE REGISTER (SYM) The system mode register, SYM (DEH, set 1), is used to enable and disable interrupt processing and control fast interrupt processing. SYM.0 is the enable and disable bit for global interrupt processing. SYM.1-SYM.4 control fast interrupt processing: SYM.1 is the enable bit; SYM.2-SYM.4 are the fast interrupt level selection bits. SYM.7 is the enable bit for the tristate external memory interface (not implemented in the S3C880A/F880A). A reset clears SYM.0, SYM.1, and SYM.7 to "0"; other bit values are undetermined. The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the SYM register. An Enable Interrupt (EI) instruction must be included in the initialization routine, which follows a reset operation, in order to enable interrupt processing. Although you can manipulate SYM.0 directly to enable and disable interrupts during the normal operation, we recommend using the EI and DI instructions for this purpose. System Mode Register (SYM) DFH, Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB External interface tri-state enable bit: 0 = Normal operation (Tri-state disabled) 1 = High inpendence (Tri-state disabled) Not used Fast interrupt level selection bits: 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 Not used IRQ6 IRQ7 Global interrupt enable bit: 0 = Disable all interrupts 1 = Enable all interrupts Fast interrupt enable bit: 0 = Disable fast interrupts 1 = Enable fast interrupts NOTE: The external interface is not implemented for the S3F880A microcontroller. Figure 5-5. System Mode Register (SYM) 5-9 INTERRUPT STRUCTURE S3C880A/F880A INTERRUPT MASK REGISTER (IMR) The interrupt mask register (IMR) is used to enable or disable interrupt processing for each of the seven interrupt levels used in the S3C880A/F880A interrupt structure, IRQ0-IRQ4, IRQ6, and IRQ7. After a reset, all the IMR register values are undetermined. Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's IMR bit to "1", interrupt processing for the level is enabled (not masked). The IMR register is mapped to the register location DDH in set 1. Bit values can be read and written by instructions using Register addressing mode. Interrupt Mask Register (IMR) DDH, Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not IRQ6 used IRQ7 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 Interrupt level enable bits: 0 = Disable interrupt level 1 = Enable interrupt level Figure 5-6. Interrupt Mask Register (IMR) 5-10 S3C880A/F880A INTERRUPT STRUCTURE INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR, is used to set the relative priorities of the seven interrupt levels used in the S3C880A/F880A interrupt structure. The IPR register is mapped to the register location FFH in set 1, bank 0. After a reset, the IPR register values are undetermined. If more than one interrupt source is active, the source with the highest priority level is serviced first. If both sources belong to the same interrupt level, the source with the lowest vector address usually has priority. (This priority is hardwired.) In order to define the relative priorities of interrupt levels, they are organized into groups and subgroups by the interrupt logic. Three interrupt groups are defined for the IPR logic (see Figure 5-7). These groups and subgroups are used only for IPR register priority definitions: Group A Group B Group C IRQ0, IRQ1 IRQ2, IRQ3, and IRQ4 IRQ6, IRQ7 Bits 7, 4, and 1 of the IPR register control the relative priority of interrupt groups A, B, and C. For example, the setting '001B' would select the group relationship B > C > A, and '101B' would select C > B > A. The functions of other IPR bit settings are as follows: -- IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts. -- IPR.2 controls interrupt group B. -- Interrupt group B has a subgroup to provide an additional priority relationship among interrupt levels 2, 3, and 4. IPR.3 defines possible subgroup B relationship. -- IPR.6 controls the relative priorities of group C interrupts. Interrupt Priority Register (IPR) FEH, Set 1, R/W MSB Group priority: D7 D4 D1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 = Undefined =B>C>A =A>B>C =B>A>C =C>A>B =C>B>A =A>C>B = Undefined .7 .6 .5 .4 .3 .2 .1 .0 LSB Group A 0 = IRQ0 > IRQ1 1 = IRQ1 > IRQ0 Group B 0 = IRQ2 > (IRQ3, IRQ4) 1 = (IRQ3, IRQ4) > IRQ2 Subgroup B 0 = IRQ3 > IRQ4 1 = IRQ4 > IRQ3 Not used Group C 0 = IRQ6 > IRQ7 1 = IRQ7 > IRQ6 Figure 5-7. Interrupt Priority Register (IPR) 5-11 INTERRUPT STRUCTURE S3C880A/F880A INTERRUPT REQUEST REGISTER (IRQ) Bit values in the interrupt request register, IRQ, are polled to determine interrupt request status for the seven interrupt levels in the S3C880A/F880A interrupt structure (IRQ0-IRQ4, IRQ6, and IRQ7). Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt is requested and a "1" indicates that an interrupt is requested for that level. The IRQ register is mapped to the register location DCH in set 1. IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. After a reset, the IRQ register is cleared to 00H. IRQ register values can be polled even if a DI instruction has been executed. If an interrupt occurs while the interrupt structure is disabled, it will not be serviced. But the interrupt request can still be detected by polling IRQ values. This can be useful in order to determine which events occurred while the interrupt structure was disabled. Interrupt Request Register (IRQ) DCH, Set 1, Read-only MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB IRQ0 IRQ2 IRQ3 IRQ4 Not used for the S3F880A. IRQ6 IRQ7 Interrupt level request pending bits: 0 = Interrupt level is not pending 1 = Interrupt level is pending IRQ1 Figure 5-8. Interrupt Request Register (IRQ) 5-12 S3C880A/F880A INTERRUPT STRUCTURE INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: one is the type that automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other is the one that must be cleared by the application program's interrupt service routine. Each interrupt level has a corresponding interrupt request bit in the IRQ register that the CPU polls for interrupt requests. Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. It then issues an IRQ pulse to tell the CPU that an interrupt is waiting to be serviced. The CPU acknowledges the interrupt source, executes the service routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or written by software. In the S3C880A/F880A interrupt structure, the P1.0, P1.1, P1.2 and P1.3 external interrupts, and the capture A interrupt belong to this category of interrupts whose pending conditions are cleared automatically by hardware. Pending Bits Cleared by the Service Routine The second type of pending bit must be cleared by program software. The service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be written to the pending bit location in the corresponding mode or control register. Pending conditions for the timer 0 match interrupt, the timer A interrupt, the OSD row interrupt and the V-sync interrupt must be cleared by the application's service routines. 5-13 INTERRUPT STRUCTURE S3C880A/F880A INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. 2. 3. 4. 5. 6. 7. A source generates an interrupt request by setting the interrupt request bit to "1". The CPU polling procedure identifies a pending condition for that source. The CPU checks the source's interrupt level. The CPU generates an interrupt acknowledge signal. Interrupt logic determines the interrupt's vector address. The service routine starts and the source's pending flag is cleared to "0" (either by hardware or by software). The CPU continues polling for interrupt requests. INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced, the following conditions must be met: -- Interrupt processing must be enabled (EI, SYM.0 = "1") -- Interrupt level must be enabled (IMR register) -- Interrupt level must have the highest priority if more than one level is currently requesting service -- Interrupt must be enabled at the interrupt's source (peripheral control register) If all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The CPU then initiates an interrupt machine cycle that completes the following processing sequence: 1. 2. 3. 4. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts. Save the program counter and status flags to stack. Branch to the interrupt vector to fetch the service routine's address. Pass control to the interrupt service routine. When the interrupt service routine is completed, an Interrupt Return instruction (IRET) occurs. The IRET restores the PC and status flags and sets SYM.0 to "1", allowing the CPU to process the next interrupt request. 5-14 S3C880A/F880A INTERRUPT STRUCTURE GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM contains the addresses of the interrupt service routine that corresponds to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. 2. 3. 4. 5. 6. Push the program counter's low-byte value to stack. Push the program counter's high-byte value to stack. Push the FLAGS register values to stack. Fetch the service routine's high-byte address from the vector address. Fetch the service routine's low-byte address from the vector address. Branch to the service routine specified by the 16-bit vector address. NOTE A 16-bit vector address always begins at an even-numbered ROM location from 00H-FFH. NESTING OF VECTORED INTERRUPTS You can nest a higher priority interrupt request while a lower priority request is being serviced. To do this, you must follow these steps: 1. 2. 3. 4. 5. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR). Load the IMR register with a new mask to enable the higher priority interrupt only. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs). When the lower-priority interrupt service routine ends, return the IMR to its original value by restoring the previous mask from the stack (POP IMR). Execute an IRET. Depending on the application, you may be able to simplify this procedure to some extent. INSTRUCTION POINTER (IP) The instruction pointer (IP) is used by all the S3C8-series microcontrollers to control optional high-speed interrupt processing called fast interrupts. The IP consists of the register pair, DAH and DBH. The IP register names are IPH (high byte, IP15-IP8) and IPL (low byte, IP7-IP0). 5-15 INTERRUPT STRUCTURE S3C880A/F880A FAST INTERRUPT PROCESSING The feature called fast interrupt processing lets designated interrupts be completed in approximately six clock cycles instead of the usual 22 clock cycles. Bit 1 of the system mode register, SYM.1, enables fast interrupt processing while SYM.2-SYM.4 are used to select a specific level for fast processing. Two other system registers support fast interrupts: -- The instruction pointer (IP) holds the starting address of the service routine (and is later used to swap the program counter values), and -- When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated register called FLAGS' (FLAGS prime). NOTE For the S3C880A/F880A microcontrollers, the service routine for any one of the seven interrupt levels (IRQ0- IRQ4, IRQ6, or IRQ7) can be designated as a fast interrupt. Procedure for Initiating Fast Interrupts To initiate fast interrupt processing, follow these steps: 1. 2. 3. Load the start address of the service routine into the instruction pointer. Load the level number into the fast interrupt select field. Write a "1" to the fast interrupt enable bit in the SYM register. Fast Interrupt Service Routine When an interrupt occurs in the level selected for fast interrupt processing, the following events occur: 1. 2. 3. 4. 5. 6. 7. The contents of the instruction pointer and the PC are swapped. The FLAGS register values are written to the dedicated FLAGS' register. The fast interrupt status bit in the FLAGS register is set. The interrupt is serviced. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction pointer and PC values are swapped back. The content of FLAGS' (FLAGS prime) is copied automatically back into the FLAGS register. The fast interrupt status bit in FLAGS is cleared automatically. Programming Guidelines Remember that the only way to enable or disable a fast interrupt is to set or clear the fast interrupt enable bit in the SYM register (SYM.1), respectively. Executing an EI or DI instruction affects only normal interrupt processing. Also, if you use fast interrupts, remember to load the IP with a new start address when the fast interrupt service routine ends. (Please refer to the programming tip on page 5-17 for an example.) 5-16 S3C880A/F880A INTERRUPT STRUCTURE F PROGRAMMING TIP -- Programming Level IRQ0 as a Fast Interrupt This example shows you how to program fast interrupt processing for a select interrupt level -- in this case, for the timer 0 (capture) interrupt, INT0: * * * LD T0CON,#52H ; Enable T0 interrupt ; Select fOSC/256 as T0 clock source LDW LD EI * * * IPH,#T0_INT SYM,#02H ; ; ; ; ; IPH high byte of interrupt service routine IPL low byte of interrupt service routine Enable fast interrupt processing Select IRQ0 for fast service Enable interrupts FAST_RET: T0_INT: * * * ; IP Address of T0_INT (again) (Fast service routine executes) * * * LD JP T0CON,#52H T,FAST_RET ; Clear T0INT interrupt pending bit 5-17 INTERRUPT STRUCTURE S3C880A/F880A NOTES 5-18 S3C880A/F880A SAM8 INSTRUCTION SET 6 OVERVIEW DATA TYPES SAM8 INSTRUCTION SET The SAM8 instruction set is designed to support a large register file. It includes a full complement of 8-bit arithmetic and logic operations, including multiplying and dividing. There are 78 instructions. No special I/O instructions are necessary because I/O control and data registers are mapped directly into the register file. Decimal adjustment is included in binary-coded decimal (BCD) operations. 16-bit word data can be incremented and decremented. Flexible instructions for bit addressing, rotate, and shift operations complete the powerful data manipulation capabilities of the SAM8 instruction set. The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can be set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least significant (right-most) bit. REGISTER ADDRESSING To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory addresses. For detailed information about register addressing, please refer to Chapter 2, "Address Spaces." ADDRESSING MODES There are seven addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please refer to chapter 3, "Addressing Modes." 6-1 SAM8 INSTRUCTION SET S3C880A/F880A Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR LD LDB LDE LDC LDED LDCD LDEI LDCI LDEPD LDCPD LDEPI LDCPI LDW POP POPUD POPUI PUSH PUSHUD PUSHUI dst dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst dst,src dst,src src dst,src dst,src Clear Load Load bit Load external data memory Load program memory Load external data memory and decrement Load program memory and decrement Load external data memory and increment Load program memory and increment Load external data memory with pre-decrement Load program memory with pre-decrement Load external data memory with pre-increment Load program memory with pre-increment Load word Pop from stack Pop user stack (decrementing) Pop user stack (incrementing) Push to stack Push user stack (decrementing) Push user stack (incrementing) 6-2 S3C880A/F880A SAM8 INSTRUCTION SET Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions ADC ADD CP DA DEC DECW DIV INC INCW MULT SBC SUB dst,src dst,src dst,src dst dst dst dst,src dst dst dst,src dst,src dst,src Add with carry Add Compare Decimal adjust Decrement Decrement word Divide Increment Increment word Multiply Subtract with carry Subtract Logic Instructions AND COM OR XOR dst,src dst dst,src dst,src Logical AND Complement Logical OR Logical exclusive OR 6-3 SAM8 INSTRUCTION SET S3C880A/F880A Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions BTJRF BTJRT CALL CPIJE CPIJNE DJNZ ENTER EXIT IRET JP JP JR NEXT RET WFI cc,dst dst cc,dst dst,src dst,src dst dst,src dst,src r,dst Bit test and jump relative on false Bit test and jump relative on true Call procedure Compare, increment and jump on equal Compare, increment and jump on non-equal Decrement register and jump on non-zero Enter Exit Interrupt return Jump on condition code Jump unconditional Jump relative on condition code Next Return Wait for interrupt Bit Manipulation Instructions BAND BCP BITC BITR BITS BOR BXOR TCM TM dst,src dst,src dst dst dst dst,src dst,src dst,src dst,src Bit AND Bit compare Bit complement Bit reset Bit set Bit OR Bit XOR Test complement under mask Test under mask 6-4 S3C880A/F880A SAM8 INSTRUCTION SET Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions RL RLC RR RRC SRA SWAP dst dst dst dst dst dst Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles CPU Control Instructions CCF DI EI IDLE NOP RCF SB0 SB1 SCF SRP SRP0 SRP1 STOP src src src Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers Set register pointer 0 Set register pointer 1 Enter Stop mode 6-5 SAM8 INSTRUCTION SET S3C880A/F880A FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of the CPU operations. Four of these bits, FLAGS.4 - FLAGS.7, can be tested and used with conditional jump instructions; two others FLAGS.2 and FLAGS.3 are used for BCD arithmetic. The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is being addressed. FLAGS is located in the system control register area of set 1 (D5H). FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two writes will occur to the Flags register, producing an unpredictable result. System Flags Register (FLAGS) D5H, Set 1, R/W MSB Carry flag (C) .7 .6 .5 .4 .3 .2 .1 .0 LSB Bank address status flag (BA) First interrupt status flag (FIS) Half-carry flag (H) Zero flag (Z) Sign flag (S) Overflow (V) Decimal adjust flag (D) Figure 6-1. System Flags Register (FLAGS) 6-6 S3C880A/F880A SAM8 INSTRUCTION SET FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag. Z Zero Flag (FLAGS.6) For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero. S V D Sign Flag (FLAGS.5) Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic zero indicates a positive number and a logic one indicates a negative number. Overflow Flag (FLAGS.4) The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than - 128. It is also cleared to "0" following logic operations. Decimal Adjust Flag (FLAGS.3) The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by programmers, and cannot be used as a test condition. H Half-Carry Flag (FLAGS.2) The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a program. FIS Fast Interrupt Status Flag (FLAGS.1) The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing. When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed. BA Bank Address Flag (FLAGS.0) The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected, bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when you execute the SB0 instruction and is set to "1" (select bank 1) when you execute the SB1 instruction. 6-7 SAM8 INSTRUCTION SET S3C880A/F880A INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag C Z S V D H 0 1 * - x Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Description Table 6-3. Instruction Set Symbols Symbol dst src @ PC IP FLAGS RP # H D B opc Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register (D5H) Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode Description 6-8 S3C880A/F880A SAM8 INSTRUCTION SET Table 6-4. Instruction Notation Conventions Notation cc r rb r0 rr R Rb RR Condition code Working register only Bit (b) of working register Bit 0 (LSB) of working register Working register pair Register or working register Bit 'b' of register or working register Register pair or working register pair Description Actual Operand Range See list of condition codes in Table 6-6. Rn (n = 0-15) Rn.b (n = 0-15, b = 0-7) Rn (n = 0-15) RRp (p = 0, 2, 4, ..., 14) reg or Rn (reg = 0-255, n = 0-15) reg.b (reg = 0-255, b = 0-7) reg or RRp (reg = 0-254, even number only, where p = 0, 2, ..., 14) addr (addr = 0-254, even number only) @Rn (n = 0-15) @Rn or @reg (reg = 0-255, n = 0-15) @RRp (p = 0, 2, ..., 14) @RRp or @reg (reg = 0-254, even only, where p = 0, 2, ..., 14) #reg[Rn] (reg = 0-255, n = 0-15) #addr[RRp] (addr = range -128 to +127, where p = 0, 2, ..., 14) #addr [RRp] (addr = range 0-65535, where p = 0, 2, ..., 14) addr (addr = range 0-65535) addr (addr = number in the range +127 to -128 that is an offset relative to the address of the next instruction) #data (data = 0-255) #data (data = range 0-65535) IA Ir IR Irr IRR Indirect addressing mode Indirect working register only Indirect register or indirect working register Indirect working register pair only Indirect register pair or indirect working register pair Indexed addressing mode Indexed (short offset) addressing mode X XS XL Indexed (long offset) addressing mode DA RA Direct addressing mode Relative addressing mode IM IML Immediate addressing mode Immediate (long) addressing mode 6-9 SAM8 INSTRUCTION SET S3C880A/F880A Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) -- U P P E R 0 1 2 3 4 5 N I B B L E 6 7 8 9 A B C H E X D E F 0 DEC R1 RLC R1 INC R1 JP IRR1 DA R1 POP R1 COM R1 PUSH R2 DECW RR1 RL R1 INCW RR1 CLR R1 RRC R1 SRA R1 RR R1 SWAP R1 1 DEC IR1 RLC IR1 INC IR1 SRP/0/1 IM DA IR1 POP IR1 COM IR1 PUSH IR2 DECW IR1 RL IR1 INCW IR1 CLR IR1 RRC IR1 SRA IR1 RR IR1 SWAP IR1 2 ADD r1,r2 ADC r1,r2 SUB r1,r2 SBC r1,r2 OR r1,r2 AND r1,r2 TCM r1,r2 TM r1,r2 PUSHUD IR1,R2 POPUD IR2,R1 CP r1,r2 XOR r1,r2 CPIJE Ir,r2,RA CPIJNE Irr,r2,RA LDCD r1,Irr2 LDCPD r2,Irr1 3 ADD r1,Ir2 ADC r1,Ir2 SUB r1,Ir2 SBC r1,Ir2 OR r1,Ir2 AND r1,Ir2 TCM r1,Ir2 TM r1,Ir2 PUSHUI IR1,R2 POPUI IR2,R1 CP r1,Ir2 XOR r1,Ir2 LDC r1,Irr2 LDC r2,Irr1 LDCI r1,Irr2 LDCPI r2,Irr1 4 ADD R2,R1 ADC R2,R1 SUB R2,R1 SBC R2,R1 OR R2,R1 AND R2,R1 TCM R2,R1 TM R2,R1 MULT R2,RR1 DIV R2,RR1 CP R2,R1 XOR R2,R1 LDW RR2,RR1 CALL IA1 LD R2,R1 CALL IRR1 LD IR2,R1 LD R2,IR1 5 ADD IR2,R1 ADC IR2,R1 SUB IR2,R1 SBC IR2,R1 OR IR2,R1 AND IR2,R1 TCM IR2,R1 TM IR2,R1 MULT IR2,RR1 DIV IR2,RR1 CP IR2,R1 XOR IR2,R1 LDW IR2,RR1 6 ADD R1,IM ADC R1,IM SUB R1,IM SBC R1,IM OR R1,IM AND R1,IM TCM R1,IM TM R1,IM MULT IM,RR1 DIV IM,RR1 CP R1,IM XOR R1,IM LDW RR1,IML LD IR1,IM LD R1,IM CALL DA1 7 BOR r0-Rb BCP r1.b, R2 BXOR r0-Rb BTJR r2.b, RA LDB r0-Rb BITC r1.b BAND r0-Rb BIT r1.b LD r1, x, r2 LD r2, x, r1 LDC r1, Irr2, xL LDC r2, Irr2, xL LD r1, Ir2 LD Ir1, r2 LDC r1, Irr2, xs LDC r2, Irr1, xs 6-10 S3C880A/F880A SAM8 INSTRUCTION SET Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) -- U P P E R 0 1 2 3 4 5 N I B B L E 6 7 8 9 A B C H E X D E F LD r1,R2 LD r2,R1 DJNZ r1,RA JR cc,RA LD r1,IM JP cc,DA INC r1 8 LD r1,R2 9 LD r2,R1 A DJNZ r1,RA B JR cc,RA C LD r1,IM D JP cc,DA E INC r1 F NEXT ENTER EXIT WFI SB0 SB1 IDLE STOP DI EI RET IRET RCF SCF CCF NOP 6-11 SAM8 INSTRUCTION SET S3C880A/F880A CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6. The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump instructions. Table 6-6. Condition Codes Binary 0000 1000 0111 (1) 1111 (1) 0110 (1) 1110 1101 0101 0100 1100 0110 (1) 1110 (1) 1001 0001 1010 0010 1111 (1) 0111 (1) 1011 0011 (1) Mnemonic F T C NC Z NZ PL MI OV NOV EQ NE GE LT GT LE UGE ULT UGT ULE Description Always false Always true Carry No carry Zero Not zero Plus Minus Overflow No overflow Equal Not equal Greater than or equal Less than Greater than Less than or equal Unsigned greater than or equal Unsigned less than Unsigned greater than Unsigned less than or equal C=1 C=0 Z=1 Z=0 S=0 S=1 V=1 V=0 Z=1 Z=0 Flags Set - - (S XOR V) = 0 (S XOR V) = 1 (Z OR (S XOR V)) = 0 (Z OR (S XOR V)) = 1 C=0 C=1 (C = 0 AND Z = 0) = 1 (C OR Z) = 1 NOTES: 1. It indicates condition codes that are related to two different mnemonics but which test the same flag. For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used; after a CP instruction, however, EQ would probably be used. 2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used. 6-12 S3C880A/F880A SAM8 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This chapter contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and fast referencing. The following information is included in each instruction description: -- -- -- -- -- -- -- -- Instruction name (mnemonic) Full instruction name Source/destination format of the instruction operand Shorthand notation of the instruction's operation Textual description of the instruction's effect Specific flag settings affected by the instruction Detailed description of the instruction's format, execution time, and addressing mode(s) Programming example(s) explaining how to use the instruction 6-13 SAM8 INSTRUCTION SET S3C880A/F880A ADC ADC -- Add with Carry dst,src dst dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. Operation: Flags: C: Z: S: V: Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D: Always cleared to "0". H: Set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. Bytes opc dst | src 2 Cycles 6 Opcode (Hex) 12 13 Addr Mode dst src r r r lr Format: opc src dst 3 10 14 15 R R R IR opc dst src 3 10 16 R IM Examples: Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: ADC ADC ADC ADC ADC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#11H R1 = 14H, R2 = 03H R1 = 1BH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 32H In the first example, the destination register R1 contains the value 10H, the carry flag is set to "1", and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and the carry flag value ("1") to the destination value 10H, leaving 14H in the register R1. 6-14 S3C880A/F880A SAM8 INSTRUCTION SET ADD -- Add ADD Operation: dst,src dst dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D: Always cleared to "0". H: Set if a carry from the low-order nibble occurred. C: Z: S: V: Format: Bytes opc dst | src 2 Cycles 6 Opcode (Hex) 02 03 Addr Mode dst src r r r lr opc src dst 3 10 04 05 R R R IR opc dst src 3 10 06 R IM Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: ADD ADD ADD ADD ADD R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H R1 = 15H, R2 = 03H R1 = 1CH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 46H In the first example, the destination working register R1 contains 12H and the source working register R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in the register R1. 6-15 SAM8 INSTRUCTION SET S3C880A/F880A AND -- Logical AND AND Operation: dst,src dst dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected. Format: Bytes opc dst | src 2 Cycles 6 Opcode (Hex) 52 53 Addr Mode dst src r r r lr opc src dst 3 10 54 55 R R R IR opc dst src 3 10 56 R IM Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: AND AND AND AND AND R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H R1 = 02H, R2 = 03H R1 = 02H, R2 = 03H Register 01H = 01H, register 02H = 03H Register 01H = 00H, register 02H = 03H Register 01H = 21H In the first example, the destination working register R1 contains the value 12H and the source working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with the destination operand value 12H, leaving the value 02H in the register R1. 6-16 S3C880A/F880A SAM8 INSTRUCTION SET BAND BAND BAND Operation: - Bit AND dst,src.b dst.b,src dst(0) dst(0) AND src(b) or dst(b) dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source). The resultant bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected. Format: Bytes opc dst | b | 0 Cycles 10 Opcode (Hex) 67 Addr Mode dst src r0 Rb src 3 opc NOTE: src | b | 1 dst 3 10 67 Rb r0 In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Examples: Given: R1 = 07H and register 01H = 05H: BAND BAND R1,01H.1 01H.1,R1 R1 = 05H, register 01H = 05H Register 01H = 05H, R1 = 07H In the first example, the source register 01H contains the value 05H (00000101B) and the destination working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1" ANDs the bit 1 value of the source register ("0") with the bit 0 value of the register R1 (destination), leaving the value 0525H (00000101B) in the register R1. 6-17 SAM8 INSTRUCTION SET S3C880A/F880A BCP BCP - Bit Compare dst,src.b dst(0) - src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison. Operation: Flags: C: Z: S: V: D: H: Unaffected. Set if the two bits are the same; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected. Format: Bytes opc NOTE: dst | b | 0 Cycles 10 Opcode (Hex) 17 Addr Mode dst src r0 Rb src 3 In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H and register 01H = 01H: BCP R1,01H.1 R1 = 07H, register 01H = 01H If the destination working register R1 contains the value 07H (00000111B) and the source register 01H contains the value 01H (00000001B), the statement "BCP R1,01H.1" compares bit one of the source register (01H) and bit zero of the destination register (R1). Because the bit values are not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H). 6-18 S3C880A/F880A SAM8 INSTRUCTION SET BITC BITC - Bit Complement dst.b dst(b) NOT dst(b) This instruction complements the specified bit within the destination without affecting any other bit in the destination. Operation: Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected. Format: Bytes opc NOTE: dst | b | 0 Cycles 8 Opcode (Hex) 57 Addr Mode dst rb 2 In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H BITC R1.1 R1 = 05H If the working register R1 contains the value 07H (00000111B), the statement "BITC R1.1" complements bit one of the destination, leaving the value 05H (00000101B) in the register R1. Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H) is cleared. 6-19 SAM8 INSTRUCTION SET S3C880A/F880A BITR BITR - Bit Reset dst.b dst(b) 0 The BITR instruction clears the specified bit within the destination without affecting any other bit in the destination. Operation: Flags: Format: No flags are affected. Bytes opc NOTE: dst | b | 0 Cycles 8 Opcode (Hex) 77 Addr Mode dst rb 2 In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H: BITR R1.1 R1 = 05H If the value of the working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one of the destination register R1, leaving the value 05H (00000101B). 6-20 S3C880A/F880A SAM8 INSTRUCTION SET BITS BITS - Bit Set dst.b dst(b) 1 The BITS instruction sets the specified bit within the destination without affecting any other bit in the destination. Operation: Flags: Format: No flags are affected. Bytes opc NOTE: dst | b | 1 Cycles 8 Opcode (Hex) 77 Addr Mode dst rb 2 In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H: BITS R1.3 R1 = 0FH If the working register R1 contains the value 07H (00000111B), the statement "BITS R1.3" sets bit three of the destination register R1 to "1", leaving the value 0FH (00001111B). 6-21 SAM8 INSTRUCTION SET S3C880A/F880A BOR BOR BOR - Bit OR dst,src.b dst.b,src dst(0) dst(0) OR src(b) or dst(b) dst(b) OR src(0) The specified bit of the source (or destination) is logically ORed with bit zero (LSB) of the destination (or source). The resulting bit value is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Operation: Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected. Format: Bytes opc dst | b | 0 Cycles 10 Opcode (Hex) 07 Addr Mode dst src r0 Rb src 3 opc NOTE: src | b | 1 dst 3 10 07 Rb r0 In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit. Examples: Given: R1 = 07H and register 01H = 03H: BOR BOR R1, 01H.1 01H.2, R1 R1 = 07H, register 01H = 03H Register 01H = 07H, R1 = 07H In the first example, the destination working register R1 contains the value 07H (00000111B) and the source register 01H the value 03H (00000011B). The statement "BOR R1,01H.1" logically ORs bit one of the register 01H (source) with bit zero of R1 (destination). This leaves the same value (07H) in the working register R1. In the second example, the destination register 01H contains the value 03H (00000011B) and the source working register R1 the value 07H (00000111B). The statement "BOR 01H.2,R1" logically ORs bit two of the register 01H (destination) with bit zero of R1 (source). This leaves the value 07H in the register 01H. 6-22 S3C880A/F880A SAM8 INSTRUCTION SET BTJRF BTJRF Operation: - Bit Test, Jump Relative on False dst,src.b If src(b) is a "0", then PC PC + dst The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRF instruction is executed. Flags: Format: No flags are affected. Bytes (1) Cycles 16/18 (2) Opcode (Hex) 37 Addr Mode dst src RA rb opc src | b | 0 dst 3 NOTES: 1. In the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. 2. Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. Example: Given: R1 = 07H: BTJRF SKIP,R1.3 PC jumps to SKIP location If the working register R1 contains the value 07H (00000111B), the statement "BTJRF SKIP,R1.3" tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to - 128.) 6-23 SAM8 INSTRUCTION SET S3C880A/F880A BTJRT BTJRT Operation: - Bit Test, Jump Relative on True dst,src.b If src(b) is a "1", then PC PC + dst The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRT instruction is executed. Flags: Format: No flags are affected. Bytes (1) Cycles 16/18 (2) Opcode (Hex) 37 Addr Mode dst src RA rb opc src | b | 1 dst 3 NOTES: 1. In the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. 2. Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. Example: Given: R1 = 07H: BTJRT SKIP,R1.1 If the working register R1 contains the value 07H (00000111B), the statement "BTJRT SKIP,R1.1" tests bit one in the source register (R1). Because it is a "1", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to - 128.) 6-24 S3C880A/F880A SAM8 INSTRUCTION SET BXOR BXOR BXOR Operation: - Bit XOR dst,src.b dst.b,src dst(0) dst(0) XOR src(b) or dst(b) dst(b) XOR src(0) The specified bit of the source (or destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected. Format: Bytes opc dst | b | 0 Cycles 10 Opcode (Hex) 27 Addr Mode dst src r0 Rb src 3 opc NOTE: src | b | 1 dst 3 10 27 Rb r0 In the second byte of the 3-byte instruction format, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Examples: Given: R1 = 07H (00000111B) and register 01H = 03H (00000011B): BXOR BXOR R1,01H.1 01H.2,R1 R1 = 05H, register 01H = 03H Register 01H = 07H, R1 = 07H In the first example, the destination working register R1 has the value 07H (00000111B) and the source register 01H has the value 03H (00000011B). The statement "BXOR R1,01H.1" exclusiveORs bit one of the register 01H (source) with bit zero of R1 (destination). The result bit value is stored in bit zero of R1, changing its value from 07H to 05H. The value of the source register 01H is unaffected. 6-25 SAM8 INSTRUCTION SET S3C880A/F880A CALL CALL Operation: - Call Procedure dst SP @SP SP @SP PC SP - 1 PCL SP -1 PCH dst The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to return to the original program flow. RET pops the top of the stack back into the program counter. Flags: Format: Bytes opc dst 3 Cycles 18 Opcode (Hex) F6 Addr Mode dst DA No flags are affected. opc dst 2 18 F4 IRR opc dst 2 20 D4 IA Examples: Given: R0 = 35H, R1 = 21H, PC = 1A47H, and SP = 0002H: CALL 3521H SP = 0000H (Memory locations 0000H = 1AH, 0001H = 4AH, where 4AH is the address that follows the instruction.) CALL CALL @RR0 #40H SP = 0000H (0000H = 1AH, 0001H = 49H) SP = 0000H (0000H = 1AH, 0001H = 49H) In the first example, if the program counter value is 1A47H and the stack pointer contains the value 0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the stack. The stack pointer now points to the memory location 0000H. The PC is then loaded with the value 3521H, the address of the first instruction in the program sequence to be executed. If the contents of the program counter and stack pointer are the same as in the first example, the statement "CALL @RR0" produces the same result except that 49H is stored in stack location 0001H (because the two-byte instruction format was used). The PC is then loaded with the value 3521H, the address of the first instruction in the program sequence to be executed. Assuming that the contents of the program counter and stack pointer are the same as in the first example, if the program address 0040H contains 35H and the program address 0041H contains 21H, the statement "CALL #40H" produces the same result as in the second example. 6-26 S3C880A/F880A SAM8 INSTRUCTION SET CCF CCF - Complement Carry Flag Operation: C NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected. Format: Bytes opc 1 Cycles 6 Opcode (Hex) EF Example: Given: The carry flag = "0": CCF If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing its value from logic zero to logic one. 6-27 SAM8 INSTRUCTION SET S3C880A/F880A CLR CLR - Clear dst dst dst XOR dst The destination location is cleared to "0". Operation: Flags: Format: No flags are affected. Bytes opc dst 2 Cycles 6 Opcode (Hex) B0 B1 Addr Mode dst R IR Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: CLR CLR 00H @01H Register 00H = 00H Register 01H = 02H, register 02H = 00H In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H. 6-28 S3C880A/F880A SAM8 INSTRUCTION SET COM COM - Complement dst dst NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Operation: Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 6 Opcode (Hex) 60 61 Addr Mode dst R IR Examples: Given: R1 = 07H and register 07H = 0F1H: COM COM R1 @R1 R1 = 0F8H R1 = 07H, register 07H = 0EH In the first example, the destination working register R1 contains the value 07H (00000111B). The statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0F8H (11111000B). In the second example, Indirect Register (IR) addressing mode is used to complement the value of the destination register 07H (11110001B), leaving the new value 0EH (00001110B). 6-29 SAM8 INSTRUCTION SET S3C880A/F880A CP CP - Compare dst,src dst - src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Operation: Flags: C: Z: S: V: D: H: Set if a "borrow" occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected. Format: Bytes opc dst | src 2 Cycles 6 Opcode (Hex) A2 A3 Addr Mode dst src r r r lr opc src dst 3 10 A4 A5 R R R IR opc dst src 3 10 A6 R IM Examples: 1. Given: R1 = 02H and R2 = 03H: CP R1,R2 Set the C and S flags The destination working register R1 contains the value 02H and the source register R2 contains the value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value (destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are "1". 2. Given: R1 = 05H and R2 = 0AH: CP JP INC LD R1,R2 UGE,SKIP R1 R3,R1 SKIP In this example, the destination working register R1 contains the value 05H which is less than the contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H remains in the working register R3. 6-30 S3C880A/F880A SAM8 INSTRUCTION SET CPIJE CPIJE Operation: - Compare, Increment, and Jump on Equal dst,src,RA If dst - src = "0", PC PC + RA Ir Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. Otherwise, the instruction immediately following the CPIJE instruction is executed. In either case, the source pointer is incremented by one before the next instruction is executed. Flags: Format: No flags are affected. Bytes opc NOTE: Cycles 16/18 Opcode (Hex) C2 Addr Mode dst src r Ir src dst RA 3 Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. Example: Given: R1 = 02H, R2 = 03H, and register 03H = 02H: CPIJE R1,@R2,SKIP R2 = 04H, PC jumps to SKIP location In this example, the working register R1 contains the value 02H, the working register R2 the value 03H, and the register 03H contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the @R2 value 02H (00000010B) to 02H (00000010B). Because the result of the comparison is equal, the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The source register (R2) is incremented by one, leaving a value of 04H. (Remember that the memory location must be within the allowed range of + 127 to - 128.) 6-31 SAM8 INSTRUCTION SET S3C880A/F880A CPIJNE CPIJNE Operation: - Compare, Increment, and Jump on Non-Equal dst,src,RA If dst - src "0", PC PC + RA Ir Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise the instruction following the CPIJNE instruction is executed. In either case the source pointer is incremented by one before the next instruction. Flags: Format: No flags are affected. Bytes opc NOTE: Cycles 16/18 Opcode (Hex) D2 Addr Mode dst src r Ir src dst RA 3 Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. Example: Given: R1 = 02H, R2 = 03H, and register 03H = 04H: CPIJNE R1,@R2,SKIP R2 = 04H, PC jumps to SKIP location The working register R1 contains the value 02H, the working register R2 (the source pointer) the value 03H, and the general register 03H contains the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts 04H (00000100B) from 02H (00000010B). Because the result of the comparison is non-equal, the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H. (Remember that the memory location must be within the allowed range of + 127 to - 128.) 6-32 S3C880A/F880A SAM8 INSTRUCTION SET DA DA - Decimal Adjust dst dst DA dst The destination operand is adjusted to form two 4-bit BCD digits after an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed. (The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits): Operation: Instruction Carry Before DA 0 0 0 Bits 4-7 Value (Hex) 0-9 0-8 0-9 A-F 9-F A-F 0-2 0-2 0-3 0-9 0-8 7-F 6-F H Flag Before DA 0 0 1 0 0 1 0 0 1 0 1 0 1 Bits 0-3 Value (Hex) 0-9 A-F 0-3 0-9 A-F 0-3 0-9 A-F 0-3 0-9 6-F 0-9 6-F Number Added to Byte 00 06 06 60 66 66 60 66 66 00 = - 00 FA = - 06 A0 = - 60 9A = - 66 Carry After DA 0 0 0 1 1 1 1 1 1 0 0 1 1 ADD ADC 0 0 0 1 1 1 0 SUB SBC 0 1 1 Flags: C: Z: S: V: D: H: Set if there was a carry from the most significant bit; cleared otherwise (see table). Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Undefined. Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 6 Opcode (Hex) 40 41 Addr Mode dst R IR 6-33 SAM8 INSTRUCTION SET S3C880A/F880A DA DA - Decimal Adjust (Continued) Given: The working register R0 contains the value 15 (BCD), working register R1 contains 27 (BCD), and address 27H contains 46 (BCD): ADD DA R1,R0 ; R1 ; C "0", H "0", Bits 4-7 = 3, bits 0-3 = C, R1 3CH R1 3CH + 06 Example: If an addition is performed using the BCD values 15 and 27, the result should be 42. The sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic: 0001 + 0010 0011 0101 0111 1100 = 15 27 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained: 0011 + 0000 0100 1100 0110 0010 = 42 Assuming the same values given above, the statements SUB DA 27H,R0 @R1 ; ; C "0", H "0", Bits 4-7 = 3, bits 0-3 = 1 @R1 31-0 leave the value 31 (BCD) in the address 27H (@R1). 6-34 S3C880A/F880A SAM8 INSTRUCTION SET DEC DEC - Decrement dst dst dst - 1 The contents of the destination operand are decremented by one. Operation: Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 6 Opcode (Hex) 00 01 Addr Mode dst R IR Examples: Given: R1 = 03H and register 03H = 10H: DEC DEC R1 @R1 R1 = 02H Register 03H = 0FH In the first example, if the working register R1 contains the value 03H, the statement "DEC R1" decrements the hexadecimal value by one, leaving the value 02H. In the second example, the statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one, leaving the value 0FH. 6-35 SAM8 INSTRUCTION SET S3C880A/F880A DECW DECW Operation: - Decrement Word dst dst dst - 1 The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 10 Opcode (Hex) 80 81 Addr Mode dst RR IR Examples: Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H: DECW DECW RR0 @R2 R0 = 12H, R1 = 33H Register 30H = 0FH, register 31H = 20H In the first example, the destination register R0 contains the value 12H and the register R1 the value 34H. The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word and decrements the value of R1 by one, leaving the value 33H. NOTE: A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW instruction. To avoid this problem, we recommend that you use DECW as shown in the following example: LOOP: DECW LD OR JR RR0 R2,R1 R2,R0 NZ,LOOP 6-36 S3C880A/F880A SAM8 INSTRUCTION SET DI DI - Disable Interrupts Operation: SYM (0) 0 Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled. Flags: Format: No flags are affected. Bytes opc 1 Cycles 6 Opcode (Hex) 8F Example: Given: SYM = 01H: DI If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the register and clears SYM.0 to "0", disabling interrupt processing. 6-37 SAM8 INSTRUCTION SET S3C880A/F880A DIV DIV - Divide (Unsigned) dst,src dst / src dst (UPPER) REMAINDER dst (LOWER) QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination. When the quotient is 28, the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect. Both operands are treated as unsigned integers. Operation: Flags: C: Z: S: V: D: H: Set if the V flag is set and the quotient is between 28 and 29 -1; cleared otherwise. Set if the divisor or quotient = "0"; cleared otherwise. Set if the MSB of quotient = "1"; cleared otherwise. Set if the quotient is 28 or if the divisor = "0"; cleared otherwise. Unaffected. Unaffected. Format: Bytes opc src dst 3 Cycles 28/12 * 28/12 * 28/12 * Opcode (Hex) 94 95 96 Addr Mode dst src RR RR RR R IR IM * Execution takes 12 cycles if divide-by-zero is attempted; otherwise it takes 28 cycles. Examples: Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H: DIV DIV DIV RR0,R2 RR0,@R2 RR0,#20H R0 = 03H, R1 = 40H R0 = 03H, R1 = 20H R0 = 03H, R1 = 80H In the first example, the destination working register pair RR0 contains the values 10H (R0) and 03H (R1), and the register R2 contains the value 40H. The statement "DIV RR0,R2" divides the 16-bit RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains the value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the destination register RR0 (R0) and the quotient in the lower half (R1). 6-38 S3C880A/F880A SAM8 INSTRUCTION SET DJNZ DJNZ Operation: - Decrement and Jump if Non-Zero r,dst rr-1 If r 0, PC PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC. The range of the relative address is +127 to -128, and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement. Flags: Format: No flags are affected. Bytes r | opc dst 2 Cycles 12 (jump taken) 10 (no jump) Opcode (Hex) rA r = 0 to F Addr Mode dst RA Example: Given: R1 = 02H and LOOP is the label of a relative address: DJNZ R1,LOOP DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the destination operand instead of a numeric relative address value. In the example, the working register R1 contains the value 02H, and LOOP is the label for a relative address. The statement "DJNZ R1, LOOP" decrements the register R1 by one, leaving the value 01H. Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative address specified by the LOOP label. NOTE: When PP = 11H or 10H and working register area is NOT in C0H-CFH, DJNZ instruction can not be used. 6-39 SAM8 INSTRUCTION SET S3C880A/F880A EI EI - Enable Interrupts Operation: SYM (0) 1 An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction. Flags: Format: No flags are affected. Bytes opc 1 Cycles 6 Opcode (Hex) 9F Example: Given: SYM = 00H: EI If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for global interrupt processing.) 6-40 S3C880A/F880A SAM8 INSTRUCTION SET ENTER ENTER Operation: - Enter SP @SP IP PC IP SP - 2 IP PC @IP IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer. The program memory word that is pointed to by the instruction pointer is loaded into the PC, and the instruction pointer is incremented by two. Flags: Format: Bytes opc 1 Cycles 20 Opcode (Hex) 1F No flags are affected. Example: The diagram below shows one example of how to use an ENTER statement. Before Address 1P 0050 Address PC 0040 40 41 42 43 Enter Address H Address L Address H Data 1F 01 10 PC 0110 Data Address 1P 0043 After Data Address 40 41 42 43 Enter Address H Address L Address H Data 1F 01 10 SP 0022 SP 0020 22 Data Stack Memory 20 21 22 IPH IPL Data Stack 00 50 110 Routine Memory 6-41 SAM8 INSTRUCTION SET S3C880A/F880A EXIT EXIT - Exit Operation: IP SP PC IP @SP SP + 2 @IP IP + 2 This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two. Flags: Format: Bytes opc 1 Cycles 22 Opcode (Hex) 2F No flags are affected. Example: The diagram below shows one example of how to use an EXIT statement. Before Address 1P 0050 Address PC 0040 50 51 SP 0022 140 20 21 22 IPH IPL Data Stack 00 50 Memory 22 Data Stack Exit 2F PCL old PCH 60 00 SP 0022 Data PC 0060 Data Address 1P 0052 After Data Address 60 Main Data Memory 6-42 S3C880A/F880A SAM8 INSTRUCTION SET IDLE IDLE - Idle Operation Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: Format: Bytes opc 1 Cycles 3 Opcode (Hex) 6F Addr Mode dst src - - No flags are affected. Example: The instruction IDLE stops the CPU clock but not the system clock. 6-43 SAM8 INSTRUCTION SET S3C880A/F880A INC INC - Increment dst dst dst + 1 The contents of the destination operand are incremented by one. Operation: Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected. Format: Bytes dst | opc 1 Cycles 6 Opcode (Hex) rE r = 0 to F Addr Mode dst r opc dst 2 6 20 21 R IR Examples: Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH: INC INC INC R0 00H @R0 R0 = 1CH Register 00H = 0DH R0 = 1BH, register 01H = 10H In the first example, if the destination working register R0 contains the value 1BH, the statement "INC R0" leaves the value 1CH in that same register. The next example shows the effect an INC instruction has on the register 00H, assuming that it contains the value 0CH. In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of the register 1BH from 0FH to 10H. 6-44 S3C880A/F880A SAM8 INSTRUCTION SET INCW INCW Operation: - Increment Word dst dst dst + 1 The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 10 Opcode (Hex) A0 A1 Addr Mode dst RR IR Examples: Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH: INCW INCW RR0 @R1 R0 = 1AH, R1 = 03H Register 02H = 10H, register 03H = 00H In the first example, the working register pair RR0 contains the value 1AH in the register R0 and 02H in the register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the value 03H in the register R1. In the second example, the statement "INCW @R1" uses Indirect Register (IR) addressing mode to increment the contents of the general register 03H from 0FFH to 00H and the register 02H from 0FH to 10H. NOTE: A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an INCW instruction. To avoid this problem, we recommend that you use INCW as shown in the following example: LOOP: INCW LD OR JR RR0 R2,R1 R2,R0 NZ,LOOP 6-45 SAM8 INSTRUCTION SET S3C880A/F880A IRET IRET - Interrupt Return IRET (Normal) FLAGS @SP SP SP + 1 PC @SP SP SP + 2 SYM(0) 1 IRET (Fast) PC IP FLAGS FLAGS' FIS 0 Operation: This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine. Flags: Format: IRET (Normal) opc IRET (Fast) opc Bytes 1 Bytes 1 Cycles 16 Cycles 6 Opcode (Hex) BF Opcode (Hex) BF All flags are restored to their original settings (that is, the settings before the interrupt occurred). Example: In the figure below, the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled. When an interrupt occurs, the program counter and the instruction pointer are swapped. This causes the PC to jump to the address 100H and the IP to keep the return address. The last instruction in the service routine normally is a jump to IRET at the address FFH. This causes the instruction pointer to be loaded with 100H "again" and the program counter to jump back to the main program. Now, the next interrupt can occur and the IP is still correct at 100H. 0H FFH 100H IRET Interrupt Service Routine JP to FFH FFFFH Note that in the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay attention to the order of the last two instructions. The IRET cannot be immediately proceeded by clearing the interrupt status (as with a reset of the IPR register). 6-46 S3C880A/F880A SAM8 INSTRUCTION SET JP JP JP - Jump cc,dst dst (Conditional) (Unconditional) Operation: If cc is true, PC dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair. Control then passes to the statement addressed by the PC. Flags: Format: (1) No flags are affected. Bytes (2) Cycles 10/12 (3) Opcode (Hex) ccD cc = 0 to F Addr Mode dst DA cc | opc dst 3 opc dst 2 10 30 IRR NOTES: 1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. In the first byte of the 3-byte instruction format (conditional jump), the condition code and the opcode are both four bits. 3. For a conditional jump, execution time is 12 cycles if the jump is taken or 10 cycles if it is not taken. Examples: Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H: JP JP C,LABEL_W @00H LABEL_W = 1000H, PC = 1000H PC = 0120H The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement "JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that location. Had the carry flag not been set, control would then have passed to the statement immediately following the JP instruction. The second example shows an unconditional JP. The statement "JP @00" replaces the contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H. 6-47 SAM8 INSTRUCTION SET S3C880A/F880A JR JR - Jump Relative cc,dst If cc is true, PC PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed. (See the list of condition codes). The range of the relative address is +127 to -128, and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement. Operation: Flags: Format: No flags are affected. Bytes (1) Cycles 10/12 (2) Opcode (Hex) ccB cc = 0 to F Addr Mode dst RA cc | opc dst 2 NOTES: 1. In the first byte of the two-byte instruction format, the condition code and the opcode are four bits each. 2. Instruction execution time is 12 cycles if the jump is taken or 10 cycles if it is not taken. Example: Given: The carry flag = "1" and LABEL_X = 1FF7H: JR C,LABEL_X PC = 1FF7H If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass control to the statement whose address is now in the PC. Otherwise, the program instruction following the JR would be executed. 6-48 S3C880A/F880A SAM8 INSTRUCTION SET LD LD - Load dst,src dst src The contents of the source are loaded into the destination. The source's contents are unaffected. Operation: Flags: Format: No flags are affected. Bytes dst | opc src 2 Cycles 6 6 Opcode (Hex) rC r8 Addr Mode dst src r r IM R src | opc dst 2 6 r9 r = 0 to F R r opc dst | src 2 6 6 C7 D7 r Ir lr r opc src dst 3 10 10 E4 E5 R R R IR opc dst src 3 10 10 E6 D6 R IR IM IM opc src dst 3 10 F5 IR R opc dst | src x 3 10 87 r x [r] opc src | dst x 3 10 97 x [r] r 6-49 SAM8 INSTRUCTION SET S3C880A/F880A LD LD - Load (Continued) Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD LD LD LD LD LD LD LD LD LD LD LD R0,#10H R0,01H 01H,R0 R1,@R0 @R0,R1 00H,01H 02H,@00H 00H,#0AH @00H,#10H @00H,02H R0 = 10H R0 = 20H, register 01H = 20H Register 01H = 01H, R0 = 01H R1 = 20H, R0 = 01H R0 = 01H, R1 = 0AH, register 01H = 0AH Register 00H = 20H, register 01H = 20H Register 02H = 20H, register 00H = 01H Register 00H = 0AH Register 00H = 01H, register 01H = 10H Register 00H = 01H, register 01H = 02H, register 02H = 02H R0 = 0FFH, R1 = 0AH Register 31H = 0AH, R0 = 01H, R1 = 0AH Examples: R0,#LOOP[R1] #LOOP[R0],R1 6-50 S3C880A/F880A SAM8 INSTRUCTION SET LDB LDB LDB - Load Bit dst,src.b dst.b,src dst(0) src(b) or dst(b) src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Operation: Flags: Format: No flags are affected. Bytes opc dst | b | 0 Cycles 10 Opcode (Hex) 47 Addr Mode dst src r0 Rb src 3 opc NOTE: src | b | 1 dst 3 10 47 Rb r0 In the second byte of the instruction format, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Examples: Given: R0 = 06H and general register 00H = 05H: LDB LDB R0,00H.2 00H.0,R0 R0 = 07H, register 00H = 05H R0 = 06H, register 00H = 04H In the first example, the destination working register R0 contains the value 06H and the source general register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the 00H register into bit zero of the R0 register, leaving the value 07H in the register R0. In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit zero of the register R0 to the specified bit (bit zero) of the destination register, leaving 04H in the general register 00H. 6-51 SAM8 INSTRUCTION SET S3C880A/F880A LDC/LDE LDC/LDE Operation: - Load Memory dst,src dst src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and an odd number for data memory. Flags: Format: No flags are affected. Bytes 1. 2. 3. 4. 5. opc opc opc opc opc dst | src 2 Cycles 12 Opcode (Hex) C3 Addr Mode dst src r Irr src | dst 2 12 D3 Irr r dst | src XS XS XLL XLL DA L DA L DA L DA L XLH XLH DA H DA H DA H DA H 3 18 E7 r XS [rr] src | dst 3 18 F7 XS [rr] r dst | src 4 20 A7 r XL [rr] 6. opc src | dst 4 20 B7 XL [rr] r 7. opc dst | 0000 4 20 A7 r DA 8. opc src | 0000 4 20 B7 DA r 9. opc dst | 0001 4 20 A7 r DA 10. opc src | 0001 4 20 B7 DA r NOTES: 1. The source (src) or the working register pair [rr] for formats 5 and 6 cannot use the register pair 0-1. 2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are one byte each. 3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are two bytes each. 4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory. 6-52 S3C880A/F880A SAM8 INSTRUCTION SET LDC/LDE LDC/LDE Examples: - Load Memory (Continued) Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: LDC R0,@RR2 ; R0 contents of program memory location 0104H ; R0 = 1AH, R2 = 01H, R3 = 04H ; R0 contents of external data memory location 0104H ; R0 = 2AH, R2 = 01H, R3 = 04H ; 11H (contents of R0) is loaded into program memory ; location 0104H (RR2), ; working registers R0, R2, R3 no change ; 11H (contents of R0) is loaded into external data memory ; location 0104H (RR2), ; working registers R0, R2, R3 no change ; R0 contents of program memory location 0105H ; (01H + RR2), ; R0 = 6DH, R2 = 01H, R3 = 04H ; R0 contents of external data memory location 0105H ; (01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H ; 11H (contents of R0) is loaded into program memory location ; 0105H (01H + 0104H) ; 11H (contents of R0) is loaded into external data memory ; location 0105H (01H + 0104H) ; R0 contents of program memory location 1104H ; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H ; R0 contents of external data memory location 1104H ; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H ; R0 contents of program memory location 1104H, R0 = 88H ; R0 contents of external data memory location 1104H, ; R0 = 98H ; 11H (contents of R0) is loaded into program memory location ; 1105H, (1105H) 11H ; 11H (contents of R0) is loaded into external data memory ; location 1105H, (1105H) 11H LDE R0,@RR2 LDC (note) @RR2,R0 LDE @RR2,R0 LDC R0,#01H[RR2] LDE R0,#01H[RR2] LDC (note) #01H[RR2],R0 LDE #01H[RR2],R0 LDC R0,#1000H[RR2] LDE R0,#1000H[RR2] LDC LDE R0,1104H R0,1104H LDC (note) 1105H,R0 LDE 1105H,R0 NOTE: These instructions are not supported by masked ROM type devices. 6-53 SAM8 INSTRUCTION SET S3C880A/F880A LDCD/LDED LDCD/LDED Operation: dst,src - Load Memory and Decrement dst src rr rr - 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected. LDCD refers to program memory and LDED refers to external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for data memory. Flags: Format: No flags are affected. Bytes opc dst | src 2 Cycles 16 Opcode (Hex) E2 Addr Mode dst src r Irr Examples: Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and external data memory location 1033H = 0DDH: LDCD R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded ; into R8 and RR6 is decremented by one ; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 RR6 - 1) LDED R8,@RR6 ; 0DDH (contents of data memory location 1033H) is loaded ; into R8 and RR6 is decremented by one (RR6 RR6 - 1) ; R8 = 0DDH, R6 = 10H, R7 = 32H 6-54 S3C880A/F880A SAM8 INSTRUCTION SET LDCI/LDEI LDCI/LDEI Operation: - Load Memory and Increment dst,src dst src rr rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected. LDCI refers to program memory and LDEI refers to external data memory. The assembler makes 'Irr' even number for program memory and odd number for data memory. Flags: Format: No flags are affected. Bytes opc dst | src 2 Cycles 16 Opcode (Hex) E3 Addr Mode dst src r Irr Examples: Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and 1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H: LDCI R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 RR6 + 1) ; R8 = 0CDH, R6 = 10H, R7 = 34H LDEI R8,@RR6 ; 0DDH (contents of data memory location 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 RR6 + 1) ; R8 = 0DDH, R6 = 10H, R7 = 34H 6-55 SAM8 INSTRUCTION SET S3C880A/F880A LDCPD/LDEPD LDCPD/ LDEPD Operation: dst,src rr rr - 1 dst src - Load Memory with Pre-Decrement These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first decremented. The contents of the source location are then loaded into the destination location. The contents of the source are unaffected. LDCPD refers to program memory and LDEPD refers to external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for external data memory. Flags: Format: Bytes opc src | dst 2 Cycles 16 Opcode (Hex) F2 Addr Mode dst src Irr r No flags are affected. Examples: Given: R0 = 77H, R6 = 30H, and R7 = 00H: LDCPD @RR6,R0 ; (RR6 RR6 - 1) ; 77H (contents of R0) is loaded into program memory location ; 2FFFH (3000H - 1H) ; R0 = 77H, R6 = 2FH, R7 = 0FFH LDEPD @RR6,R0 ; (RR6 RR6 - 1) ; 77H (contents of R0) is loaded into external data memory location 2FFFH (3000H - 1H) ; R0 = 77H, R6 = 2FH, R7 = 0FFH ; 6-56 S3C880A/F880A SAM8 INSTRUCTION SET LDCPI/LDEPI LDCPI/ LDEPI Operation: dst,src - Load Memory with Pre-Increment rr rr + 1 dst src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented. The contents of the source location are loaded into the destination location. The contents of the source are unaffected. LDCPI refers to program memory and LDEPI refers to external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for data memory. Flags: Format: No flags are affected. Bytes opc src | dst 2 Cycles 16 Opcode (Hex) F3 Addr Mode dst src Irr r Examples: Given: R0 = 7FH, R6 = 21H, and R7 = 0FFH: LDCPI @RR6,R0 ; (RR6 RR6 + 1) ; 7FH (contents of R0) is loaded into program memory ; location 2200H (21FFH + 1H) ; R0 = 7FH, R6 = 22H, R7 = 00H LDEPI @RR6,R0 ; (RR6 RR6 + 1) ; 7FH (contents of R0) is loaded into external data memory ; location 2200H (21FFH + 1H) ; R0 = 7FH, R6 = 22H, R7 = 00H 6-57 SAM8 INSTRUCTION SET S3C880A/F880A LDW LDW - Load Word dst,src dst src The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Operation: Flags: Format: No flags are affected. Bytes opc src dst 3 Cycles 10 10 Opcode (Hex) C4 C5 Addr Mode dst src RR RR RR IR opc dst src 4 12 C6 RR IML Examples: Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH, register 01H = 02H, register 02H = 03H, and register 03H = 0FH: LDW LDW RR6,RR4 00H,02H R6 = 06H, R7 = 1CH, R4 = 06H, R5 = 1CH Register 00H = 03H, register 01H = 0FH, register 02H = 03H, register 03H = 0FH R2 = 03H, R3 = 0FH, Register 04H = 03H, register 05H = 0FH R6 = 12H, R7 = 34H Register 02H = 0FH, register 03H = 0EDH LDW LDW LDW LDW RR2,@R7 04H,@01H RR6,#1234H 02H,#0FEDH In the second example, please note that the statement "LDW 00H,02H" loads the contents of the source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in the general register 00H and the value 0FH in the register 01H. Other examples show how to use the LDW instruction with various addressing modes and formats. 6-58 S3C880A/F880A SAM8 INSTRUCTION SET MULT MULT Operation: - Multiply (Unsigned) dst,src dst dst x src The 8-bit destination operand (the even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. Both operands are treated as unsigned integers. Flags: C: Z: S: V: D: H: Set if the result is > 255; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if MSB of the result is a "1"; cleared otherwise. Cleared. Unaffected. Unaffected. Format: Bytes opc src dst 3 Cycles 24 24 24 Opcode (Hex) 84 85 86 Addr Mode dst src RR RR RR R IR IM Examples: Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H: MULT MULT MULT 00H, 02H Register 00H = 01H, register 01H = 20H, register 02H = 09H Register 00H = 00H, register 01H = 0C0H Register 00H = 06H, register 01H = 00H 00H, @01H 00H, #30H In the first example, the statement "MULT 00H,02H" multiplies the 8-bit destination operand (in the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The 16-bit product, 0120H, is stored in the register pair 00H, 01H. 6-59 SAM8 INSTRUCTION SET S3C880A/F880A NEXT NEXT Operation: - Next PC @IP IP IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two. Flags: Format: No flags are affected. Bytes opc 1 Cycles 14 Opcode (Hex) 0F Example: The following diagram shows one example of how to use the NEXT instruction. Before Address 1P 0043 Address PC 0120 43 44 45 Address H Address L Address H Data 01 10 PC 0130 Data Address 1P 0045 After Data Address 43 44 45 Address H Address L Address H Data 120 Next Memory 130 Routine Memory 6-60 S3C880A/F880A SAM8 INSTRUCTION SET NOP NOP - No Operation Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. No flags are affected. Flags: Format: Bytes opc 1 Cycles 6 Opcode (Hex) FF Example: When the instruction NOP is encountered in a program, no operation occurs. Instead, there happens a delay in instruction execution. 6-61 SAM8 INSTRUCTION SET S3C880A/F880A OR OR - Logical OR dst,src dst dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. Operation: Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected. Format: Bytes opc dst | src 2 Cycles 6 6 Opcode (Hex) 42 43 Addr Mode dst src r r r lr opc src dst 3 10 10 44 45 R R R IR opc dst src 3 10 46 R IM Examples: Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H = 8AH: OR OR OR OR OR R0,R1 R0,@R2 00H,01H 01H,@00H 00H,#02H R0 = 3FH, R1 = 2AH R0 = 37H, R2 = 01H, register 01H = 37H Register 00H = 3FH, register 01H = 37H Register 00H = 08H, register 01H = 0BFH Register 00H = 0AH In the first example, if the working register R0 contains the value 15H and the register R1 the value 2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in the destination register R0. Other examples show the use of the logical OR instruction with the various addressing modes and formats. 6-62 S3C880A/F880A SAM8 INSTRUCTION SET POP POP - Pop From Stack dst dst @SP SP SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Operation: Flags: Format: No flags affected. Bytes opc dst 2 Cycles 10 10 Opcode (Hex) 50 51 Addr Mode dst R IR Examples: Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH, and stack register 0FBH = 55H: POP POP 00H @00H Register 00H = 55H, SP = 00FCH Register 00H = 01H, register 01H = 55H, SP = 00FCH In the first example, the general register 00H contains the value 01H. The statement "POP 00H" loads the contents of the location 00FBH (55H) into the destination register 00H and then increments the stack pointer by one. The register 00H then contains the value 55H and the SP points to the location 00FCH. 6-63 SAM8 INSTRUCTION SET S3C880A/F880A POPUD POPUD Operation: - Pop User Stack (Decrementing) dst,src dst src IR IR - 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented. Flags: Format: No flags are affected. Bytes opc src dst 3 Cycles 10 Opcode (Hex) 92 Addr Mode dst src R IR Example: Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH, and register 02H = 70H: POPUD 02H,@00H Register 00H = 41H, register 02H = 6FH, register 42H = 6FH If the general register 00H contains the value 42H and the register 42H the value 6FH, the statement "POPUD 02H,@00H" loads the contents of the register 42H into the destination register 02H. The user stack pointer is then decremented by one, leaving the value 41H. 6-64 S3C880A/F880A SAM8 INSTRUCTION SET POPUI POPUI Operation: - Pop User Stack (Incrementing) dst,src dst src IR IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented. Flags: Format: No flags are affected. Bytes opc src dst 3 Cycles 10 Opcode (Hex) 93 Addr Mode dst src R IR Example: Given: Register 00H = 01H and register 01H = 70H: POPUI 02H,@00H Register 00H = 02H, register 01H = 70H, register 02H = 70H If the general register 00H contains the value 01H and the register 01H the value 70H, the statement "POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user stack pointer (register 00H) is then incremented by one, changing its value from 01H to 02H. 6-65 SAM8 INSTRUCTION SET S3C880A/F880A PUSH PUSH Operation: - Push to Stack src SP SP - 1 @SP src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. Flags: Format: No flags are affected. Bytes opc src 2 Cycles 10 (internal clock) 12 (external clock) 12 (internal clock) 14 (external clock) Opcode (Hex) 70 Addr Mode dst R 71 IR Examples: Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H: PUSH 40H Register 40H = 4FH, stack register 0FFH = 4FH, SPH = 0FFH, SPL = 0FFH PUSH @40H Register 40H = 4FH, register 4FH = 0AAH, stack register 0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH In the first example, if the stack pointer contains the value 0000H, and the general register 40H the value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It then loads the contents of the register 40H into the location 0FFFFH and adds this new value to the top of the stack. 6-66 S3C880A/F880A SAM8 INSTRUCTION SET PUSHUD PUSHUD Operation: - Push User Stack (Decrementing) dst,src IR IR - 1 dst src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer. Flags: Format: No flags are affected. Bytes opc dst src 3 Cycles 10 Opcode (Hex) 82 Addr Mode dst src IR R Example: Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH: PUSHUD @00H,01H Register 00H = 02H, register 01H = 05H, register 02H = 05H If the user stack pointer (register 00H, for example) contains the value 03H, the statement "PUSHUD @00H,01H" decrements the user stack pointer by one, leaving the value 02H. The 01H register value, 05H, is then loaded into the register addressed by the decremented user stack pointer. 6-67 SAM8 INSTRUCTION SET S3C880A/F880A PUSHUI PUSHUI Operation: - Push User Stack (Incrementing) dst,src IR IR + 1 dst src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer. Flags: Format: No flags are affected. Bytes opc dst src 3 Cycles 10 Opcode (Hex) 83 Addr Mode dst src IR R Example: Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH: PUSHUI @00H,01H Register 00H = 04H, register 01H = 05H, register 04H = 05H If the user stack pointer (register 00H, for example) contains the value 03H, the statement "PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. The 01H register value, 05H, is then loaded into the location addressed by the incremented user stack pointer. 6-68 S3C880A/F880A SAM8 INSTRUCTION SET RCF RCF - Reset Carry Flag RCF C0 The carry flag is cleared to logic zero, regardless of its previous value. Operation: Flags: C: Cleared to "0". No other flags are affected. Format: Bytes opc 1 Cycles 6 Opcode (Hex) CF Example: Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero. 6-69 SAM8 INSTRUCTION SET S3C880A/F880A RET RET - Return Operation: PC @SP SP SP + 2 The RET instruction is normally used to return to the previously executed procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement that is executed is the one that is addressed by the new program counter value. Flags: Format: No flags are affected. Bytes opc 1 Cycles 14 Opcode (Hex) AF Example: Given: SP = 00FCH, (SP) = 101AH, and PC = 1234: RET PC = 101AH, SP = 00FEH The statement "RET" pops the contents of the stack pointer location 00FCH (10H) into the high byte of the program counter. The stack pointer then pops the value in the location 00FEH (1AH) into the PC's low byte and the instruction at the location 101AH is executed. The stack pointer now points to the memory location 00FEH. 6-70 S3C880A/F880A SAM8 INSTRUCTION SET RL RL - Rotate Left dst C dst (7) dst (0) dst (7) dst (n + 1) dst (n), n = 0-6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag. Operation: 7 C 0 Flags: C: Z: S: V: D: H: Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 6 6 Opcode (Hex) 90 91 Addr Mode dst R IR Examples: Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H: RL RL 00H @01H Register 00H = 55H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0" In the first example, if the general register 00H contains the value 0AAH (10101010B), the statement "RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and setting the carry and overflow flags. 6-71 SAM8 INSTRUCTION SET S3C880A/F880A RLC RLC - Rotate Left Through Carry dst dst (0) C C dst (7) dst (n + 1) dst (n), n = 0-6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero. Operation: 7 C 0 Flags: Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected. C: Z: S: V: Format: Bytes opc dst 2 Cycles 6 6 Opcode (Hex) 10 11 Addr Mode dst R IR Examples: Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0": RLC RLC 00H @01H Register 00H = 54H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0" In the first example, if the general register 00H has the value 0AAH (10101010B), the statement "RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of the register 00H, leaving the value 55H (01010101B). The MSB of the register 00H resets the carry flag to "1", setting the overflow flag. 6-72 S3C880A/F880A SAM8 INSTRUCTION SET RR RR - Rotate Right dst C dst (0) dst (7) dst (0) dst (n) dst (n + 1), n = 0-6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C). Operation: 7 C 0 Flags: Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected. C: Z: S: V: Format: Bytes opc dst 2 Cycles 6 6 Opcode (Hex) E0 E1 Addr Mode dst R IR Examples: Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H: RR RR 00H @01H Register 00H = 98H, C = "1" Register 01H = 02H, register 02H = 8BH, C = "1" In the first example, if the general register 00H contains the value 31H (00110001B), the statement "RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the C flag to "1" and the sign flag and overflow flag are also set to "1". 6-73 SAM8 INSTRUCTION SET S3C880A/F880A RRC RRC - Rotate Right Through Carry dst dst (7) C C dst (0) dst (n) dst (n + 1), n = 0-6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB). Operation: 7 C 0 Flags: Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0" cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected. C: Z: S: V: Format: Bytes opc dst 2 Cycles 6 6 Opcode (Hex) C0 C1 Addr Mode dst R IR Examples: Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0": RRC RRC 00H @01H Register 00H = 2AH, C = "1" Register 01H = 02H, register 02H = 0BH, C = "1" In the first example, if the general register 00H contains the value 55H (01010101B), the statement "RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH (00101010B) in the destination register 00H. The sign flag and the overflow flag are both cleared to "0". 6-74 S3C880A/F880A SAM8 INSTRUCTION SET SB0 SB0 - Select Bank 0 Operation: BANK 0 The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file. Flags: Format: No flags are affected. Bytes opc 1 Cycles 6 Opcode (Hex) 4F Example: The statement SB0 clears FLAGS.0 to "0", selecting bank 0 register addressing. 6-75 SAM8 INSTRUCTION SET S3C880A/F880A SB1 SB1 - Select Bank 1 Operation: BANK 1 The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some KS88-series microcontrollers.) Flags: Format: No flags are affected. Bytes opc 1 Cycles 6 Opcode (Hex) 5F Example: The statement SB1 sets FLAGS.0 to "1", selecting bank 1 register addressing, if implemented. 6-76 S3C880A/F880A SAM8 INSTRUCTION SET SBC SBC - Subtract with Carry dst,src dst dst - src - c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. Operation: Flags: Set if a borrow occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise. D: Always set to "1". H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow". C: Z: S: V: Format: Bytes opc dst | src 2 Cycles 6 6 Opcode (Hex) 32 33 Addr Mode dst src r r r lr opc src dst 3 10 10 34 35 R R R IR opc dst src 3 10 36 R IM Examples: Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: SBC SBC SBC SBC SBC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#8AH R1 = 0CH, R2 = 03H R1 = 05H, R2 = 03H, register 03H = 0AH Register 01H = 1CH, register 02H = 03H Register 01H = 15H,register 02H = 03H, register 03H = 0AH Register 01H = 95H; C, S, and V = "1" In the first example, if the working register R1 contains the value 10H and the register R2 the value 03H, the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the destination (10H) and then stores the result (0CH) in the register R1. 6-77 SAM8 INSTRUCTION SET S3C880A/F880A SCF SCF - Set Carry Flag Operation: C1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes opc 1 Cycles 6 Opcode (Hex) DF Example: The statement SCF sets the carry flag to logic one. 6-78 S3C880A/F880A SAM8 INSTRUCTION SET SRA SRA - Shift Right Arithmetic dst dst (7) dst (7) C dst (0) dst (n) dst (n + 1), n = 0-6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into the bit position 6. Operation: 7 C 6 0 Flags: C: Z: S: V: D: H: Set if the bit shifted from the LSB position (bit zero) was "1". Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Always cleared to "0". Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 6 6 Opcode (Hex) D0 D1 Addr Mode dst R IR Examples: Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1": SRA SRA 00H @02H Register 00H = 0CDH, C = "0" Register 02H = 03H, register 03H = 0DEH, C = "0" In the first example, if the general register 00H contains the value 9AH (10011010B), the statement "SRA 00H" shifts the bit values in the register 00H right one bit position. Bit zero ("0") clears the C flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value 0CDH (11001101B) in the destination register 00H. 6-79 SAM8 INSTRUCTION SET S3C880A/F880A SRP/SRP0/SRP1 SRP SRP0 SRP1 Operation: src src src - Set Register Pointer If src (1) = 1 and src (0) = 0 then: If src (1) = 0 and src (0) = 1 then: If src (1) = 0 and src (0) = 0 then: RP0 (3-7) RP1 (3-7) RP0 (4-7) RP0 (3) RP1 (4-7) RP1 (3) src (3-7) src (3-7) src (4-7), 0 src (4-7), 1 The source data bits one and zero (LSB) determine whether to write one or both of the register pointers, RP0 and RP1. Bits 3-7 of the selected register pointer are written unless both register pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one. Flags: Format: Bytes opc src 2 Cycles 6 Opcode (Hex) 31 Addr Mode src IM No flags are affected. Examples: The statement SRP #40H sets the register pointer 0 (RP0) at location 0D6H to 40H and the register pointer 1 (RP1) at location 0D7H to 48H. The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to 68H. 6-80 S3C880A/F880A SAM8 INSTRUCTION SET STOP STOP Operation: - Stop Operation The STOP instruction stops both the CPU clock and the system clock causing the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released only by an external reset operation. For the reset operation, the nRESET pin must be held to Low level until the required oscillation stabilization interval has elapsed. Flags: Format: Bytes opc 1 Cycles 3 Opcode (Hex) 7F Addr Mode dst src - - No flags are affected. Example: The statement STOP halts all microcontroller operations. 6-81 SAM8 INSTRUCTION SET S3C880A/F880A SUB SUB - Subtract dst,src dst dst - src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand. Operation: Flags: C: Z: S: V: Set if a "borrow" occurred; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. D: Always set to "1". H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow". Format: Bytes opc dst | src 2 Cycles 6 6 Opcode (Hex) 22 23 Addr Mode dst src r r r lr opc src dst 3 10 10 24 25 R R R IR opc dst src 3 10 26 R IM Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: SUB SUB SUB SUB SUB SUB R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#90H 01H,#65H R1 = 0FH, R2 = 03H R1 = 08H, R2 = 03H Register 01H = 1EH, register 02H = 03H Register 01H = 17H, register 02H = 03H Register 01H = 91H; C, S, and V = "1" Register 01H = 0BCH; C and S = "1", V = "0" In the first example, if the working register R1 contains the value 12H and the register R2 contains the value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value (12H), storing the result (0FH) in the destination register R1. 6-82 S3C880A/F880A SAM8 INSTRUCTION SET SWAP SWAP Operation: - Swap Nibbles dst dst (0 - 3) dst (4 - 7) The contents of the lower four bits and the upper four bits of the destination operand are swapped. 7 43 0 Flags: C: Z: S: V: D: H: Undefined. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Undefined. Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 8 8 Opcode (Hex) F0 F1 Addr Mode dst R IR Examples: Given: Register 00H = 3EH, register 02H = 03H, and register 03H = 0A4H: SWAP SWAP 00H @02H Register 00H = 0E3H Register 02H = 03H, register 03H = 4AH In the first example, if the general register 00H contains the value 3EH (00111110B), the statement "SWAP 00H" swaps the lower and the upper four bits (nibbles) in the 00H register, leaving the value 0E3H (11100011B). 6-83 SAM8 INSTRUCTION SET S3C880A/F880A TCM TCM - Test Complement under Mask dst,src (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. Operation: Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected. Format: Bytes opc dst | src 2 Cycles 6 6 Opcode (Hex) 62 63 Addr Mode dst src r r r lr opc src dst 3 10 10 64 65 R R R IR opc dst src 3 10 66 R IM Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TCM TCM TCM TCM TCM R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#34 R0 = 0C7H, R1 = 02H, Z = "1" R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, register 01H = 02H, Z = "1" Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "1" Register 00H = 2BH, Z = "0" In the first example, if the working register R0 contains the value 0C7H (11000111B) and the register R1 the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can be tested to determine the result of the TCM operation. 6-84 S3C880A/F880A SAM8 INSTRUCTION SET TM TM - Test under Mask dst,src dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. Operation: Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected. Format: Bytes opc dst | src 2 Cycles 6 6 Opcode (Hex) 72 73 Addr Mode dst src r r r lr opc src dst 3 10 10 74 75 R R R IR opc dst src 3 10 76 R IM Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TM TM TM TM TM R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H R0 = 0C7H, R1 = 02H, Z = "0" R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, register 01H = 02H, Z = "0" Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, Z = "1" In the first example, if the working register R0 contains the value 0C7H (11000111B) and the register R1 the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation. 6-85 SAM8 INSTRUCTION SET S3C880A/F880A WFI WFI - Wait for Interrupt Operation: The CPU is effectively halted until an interrupt occurs, except in the case that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt . Flags: Format: Bytes opc 1 Cycles 6n ( n = 1, 2, 3, ... ) Opcode (Hex) 3F No flags are affected. Example: The following sample program structure shows the sequence of operations that follow a "WFI" statement: Main program . . . EI WFI (Next instruction) (Enable global interrupt) (Wait for interrupt) . . . Interrupt occurs Interrupt service routine . . . Clear interrupt flag IRET Service routine completed 6-86 S3C880A/F880A SAM8 INSTRUCTION SET XOR XOR - Logical Exclusive OR dst,src dst dst XOR src The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. Operation: Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected. Format: Bytes opc dst | src 2 Cycles 6 6 Opcode (Hex) B2 B3 Addr Mode dst src r r r lr opc src dst 3 10 10 B4 B5 R R R IR opc dst src 3 10 B6 R IM Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: XOR XOR XOR XOR XOR R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H R0 = 0C5H, R1 = 02H R0 = 0E4H, R1 = 02H, register 02H = 23H Register 00H = 29H, register 01H = 02H Register 00H = 08H, register 01H = 02H, register 02H = 23H Register 00H = 7FH In the first example, if the working register R0 contains the value 0C7H and the register R1 contains the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value, storing the result (0C5H) in the destination register R0. 6-87 SAM8 INSTRUCTION SET S3C880A/F880A NOTES 6-88 S3C880A/F880A CLOCK CIRCUITS 7 OVERVIEW CLOCK CIRCUITS The clock frequency generated by an external crystal or ceramic resonator may range from 0.5 MHz to 8 MHz. The maximum CPU clock frequency is 8 MHz. The XIN and XOUT pins connect the external oscillation source to the onchip clock circuit. A separate external L-C resonator circuit generates a clock pulse for the on-screen display (OSD) block. SYSTEM CLOCK CIRCUIT The system clock circuit has the following components: -- External crystal or ceramic oscillation source -- Oscillator stop and wake-up functions -- Programmable frequency divider for the CPU clock (fOSC divided by 1, 2, 8, or 16) -- Clock circuit control register, CLKCON C1 XIN S3C880A/F880A C2 XOUT NOTE: In X IN, XOUT pin, 10 pF load capacitor is built-in. Figure 7-1. Main Oscillator Circuit (External Crystal or Ceramic Resonator) 7-1 CLOCK CIRCUITS S3C880A/F880A CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect system clock oscillation as follows: -- In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset operation or by an external interrupt (with RC-delay noise filter). -- In Idle mode, the internal clock signal is gated off to the CPU and to all peripherals except for the OSD block, Timer A counter, PWM, and capture (CAPA), which are inactive. Idle mode is released by a reset or by all interrupt. CLKCON.5, .6 Stop Instruction CLKCON.3, .4 CLKCON.0-.2 3-Bit Signature Code (2) Oscillator Stop Main OSC Oscillator Wake-up Noise Filter 1/2 1/8 1/16 M U X M U X CPU Clock CLKCON.7 INT Pin (1) NOTES: 1. An external interrupt (with RC-delay noise filter) can be used to release Stop mode and "wake up" the main oscillator. This interrupt type includes INT0-INT3 and CAPA input. 2. For S3F880A, the CLKCON signature code (CLKCON.0-CLKCON.2) should not be '101B' (because no subsystem clock is implemented) Figure 7-2. System Clock Circuit Diagram 7-2 S3C880A/F880A CLOCK CIRCUITS SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in set 1 at address D4H. It is read/write addressable and has the following functions: -- Oscillator IRQ wake-up function enable/disable -- Main oscillator stop control -- Oscillator frequency divide-by value: non-divided, 2, 8, or 16 -- System clock signal selection The CLKCON register controls whether or not an external interrupt can be used to trigger a power-down mode release. (This is called the "IRQ wake-up" function.) The IRQ wake-up enable bit is CLKCON.7. After a reset, the external interrupt oscillator wake-up bit is set to "1", the main oscillator is activated, and the fOSC/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed to fOSC, fOSC/2, or fOSC/8. For the S3C880A/F880A, the CLKCON.0-CLKCON.2 system clock signature code should be any value other than '101B'. (This setting is invalid because a subsystem clock is not implemented.) The reset value for the clock signature code is '000B'. System Clock Control Register (CLKCON) D4H, Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Oscillator IRQ wake-up enable bit: 0 = Enable IRQ for main system oscillator wake-up in power-down mode 1 = Disable IRQ for main system Oscillator wake-up in power-down mode System clock selection bits: (note) 101B = Invalid selection Other value = Normal operating mode Divide-by selection bits for CPU clock frequency: 00 = fOSC/16 01 = fOSC/8 10 = fOSC/2 11 = fOSC/(non-divided) Main oscillator stop control bits:(note) 00 = No effect 01 = No effect 10 = Stop main oscillator 11 = No effect NOTE: Not used in S3C880A. These setting is valid in subsystem clock operation. S3C880A is not implemented subsystem operation function. Figure 7-3. System Clock Control Register (CLKCON) 7-3 CLOCK CIRCUITS S3C880A/F880A L-C Oscillator Circuit The L-C oscillator circuit has the following components: -- External L-C oscillator with a 5-8 MHz frequency range -- Oscillator clock divider value (CHACON.4 and CHACON.5) -- OSCIN and OSCOUT pins -- On/off control bit (DSPCON.0) Red-green-blue (RGB) color outputs, as well as display rates and positions, are determined by the L-C clock signal. This signal is scaled by the dot and column counter. The clock signal equals to the OSD oscillator clock divided by the clock divider value. The clock divider value is determined by the horizontal character size settings in the CHACON register. The rate at which each new display line is generated is determined strictly by the H-sync input. The rate at which each new frame (screen) is generated is determined by the V-sync input. NOTE: For stable on screen display operation, the CPU clock frequency should faster than L-C (OSD) clock. C1 = 20 pF OSCIN L S3C880A/F880A C2 = 20 pF OSDOUT Figure 7-4. L-C Oscillator Circuit for OSD 7-4 S3C880A/F880A CLOCK CIRCUITS L-C oscillator Operating Condition To operate the LC oscillator, the following conditions must be satisfied. -- LC oscillator operation must be enabled by setting DSPCON.0 to "1". -- V-sync signal and H-sync signal must be input. -- LC oscillator must be operated except at the range of H-sync blanking and V-sync blanking. H-sync Blanking Range V-sync Blanking Range V-sync Signal H-sync Signal L-C OSC on L-C OSC off RELATION BETWEEN L-C OSCILLATOR AND CPU CLOCK For normal On Screen Display, L-C oscillator less than CPU Clock + 10 % is better. For 8 MHz CPU clock, an active L-C oscillator clock range is lower than 9MHz. 7-5 CLOCK CIRCUITS S3C880A/F880A NOTES 7-6 S3C880A/F880A nRESET and POWER-DOWN 8 OVERVIEW nRESET and POWER-DOWN SYSTEM nRESET During a power-on reset, the voltage at VDD is High level and the nRESET pin is forced to Low level. The nRESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock. This brings the S3C880A/F880A into a normal operating status. The nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal CPU clock oscillation to stabilize. The minimum time required for oscillation stabilization for a reset is 1 millisecond. When a reset occurs during the normal operation (that is, when VDD and nRESET are High level), the nRESET pin is forced Low and the reset operation starts. All system and peripheral control registers are set to their default hardware reset values (see Table 8-1). In summary, the following sequence of events occurs during a reset operation: -- All interrupts are disabled. -- The watchdog function (basic timer) is enabled. -- Ports P0.0-P0.5, P1.6-P1.7 and P2are set to input mode, and P0.6-P0.7, P1.0-P1.5 and P3, these ports set to N-channel open-drain output mode. -- Peripheral control and data registers are disabled and reset to their initial control values. -- The program counter is loaded with the ROM's reset address, 0100H. -- When the programmed oscillation stabilization time interval has elapsed, the instruction stored in the ROM location 0100H (and 0101H) is fetched and executed. NOTE You can program the duration of the oscillation stabilization interval by making the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, you if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010B' to the upper nibble of BTCON. 8-1 nRESET and POWER-DOWN S3C880A/F880A HARDWARE RESET VALUES Tables 8-1 through 8-3 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers after a reset operation. The following notation is used to represent reset values: -- A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. -- An 'x' means that the bit value is undefined after a reset. -- A dash ('-') means that the bit is either not used or not mapped. Table 8-1. Set 1 Register Values after a Reset Register Name Mnemonic Address Dec Timer 0 counter Timer 0 data register Timer 0 control register Basic timer control register Clock control register System flags register Register pointer 0 Register pointer 1 Stack pointer (high byte) Stack pointer (low byte) Instruction pointer (high byte) Instruction pointer (low byte) Interrupt request register Interrupt mask register System mode register Register page pointer NOTE: Bit Values After a Reset 7 0 1 0 0 0 x 1 1 x x x x 0 x 0 0 6 0 1 0 0 0 x 1 1 x x x x 0 x - 0 5 0 1 0 0 0 x 0 0 x x x x - - 0 0 4 0 1 0 0 0 x 0 0 x x x x 0 x x 0 3 0 1 0 0 0 x 0 1 x x x x 0 x x 0 2 0 1 0 0 0 x - - x x x x 0 x x 0 1 0 1 0 0 0 0 - - x x x x 0 x 0 0 0 0 1 0 0 0 0 - - x x x x 0 x 0 0 Hex D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH T0CNT T0DATA T0CON BTCON CLKCON FLAGS RP0 RP1 SPH SPL IPH IPL IRQ IMR SYM PP 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 Although it is not used for the S3C880A/F880A, bit 5 of the SYM register should always be "0". If this bit is accidentally written to "1" by software, a system malfunction may occur. 8-2 S3C880A/F880A nRESET and POWER-DOWN Table 8-2. Set 1, Bank 0 Register Values after a Reset Register Name Mnemonic Address Dec Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 0 control register (high byte) Port 0 control register (low byte) Port 1 control register (high byte) Port 1 control register (low byte) Port 2 control register (high byte) Port 2 control register (low byte) P0 P1 P2 P3 P0CONH P0CONL P1CONH P1CONL P2CONH P2CONL 224 225 226 227 228 229 230 231 232 233 Hex E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H 7 0 0 0 - 1 0 0 1 0 0 6 0 0 0 - 1 0 0 1 0 0 Bit Values After a Reset 5 0 0 0 - 1 0 0 1 0 0 4 0 0 0 - 1 0 0 1 0 0 3 0 0 0 - 0 0 1 1 0 0 2 0 0 0 - 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 Location EAH in set 1, bank 0, are not mapped. Port 3 control register (low byte) P3CONL 235 EBH - - - - 1 1 1 1 Locations ECH-EFH in set 1, bank 0, are not mapped. Timer A data register TADATA 240 F0H 0 0 0 0 0 0 0 0 Location F1H in set 1, bank 0, are not mapped. Timer A control register STOP control register PWM0 data register (main byte) PWM0 data register (extension byte) PWM1 data register (main byte) PWM1 data register (extension byte) PWM control register Capture A data register A/D converter control register A/D conversion data register TACON STCON PWM0 PWM0EX PWM1 PWM1EX PWMCON CAPA ADCON ADDATA 242 238 244 245 246 247 248 249 250 251 F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH 0 0 1 0 1 0 0 0 - x 0 0 1 0 1 0 0 0 - x 0 0 1 0 1 0 0 0 0 x 0 0 1 0 1 0 0 0 0 x 0 0 1 0 1 0 0 0 x x 0 0 1 0 1 0 - 0 0 x 0 0 1 - 1 - 0 0 0 x - 0 1 - 1 - 0 0 0 x Location FCH in set 1, bank 0, are not mapped. Basic timer counter External memory timing register Interrupt priority register BTCNT EMT IPR 253 254 255 FDH FEH FFH 0 0 x 0 0 x 0 0 - 0 0 x 0 0 x 0 0 x 0 0 x 0 - x 8-3 nRESET and POWER-DOWN S3C880A/F880A Table 8-2. Set 1, Bank 1 Register Values after a Reset Register Name Mnemonic Address Dec OSD fringe/border control register 1 OSD fringe/border control register 2 OSD smooth control register 1 OSD smooth control register 2 OSD space color control register OSD field control register OSD palette color mode R 1 OSD palette color mode R 2 OSD palette color mode G 1 OSD palette color mode G 2 OSD palette color mode B 1 OSD palette color mode B 2 OSDFRG1 OSDFRG2 OSDSMH1 OSDSMH2 OSDCOL OSDFLD OSDPLTR1 OSDPLTR2 OSDPLTG1 OSDPLTG2 OSDPLTB1 OSDPLTB2 224 225 226 227 236 237 230 231 232 233 234 235 Hex E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH 7 0 0 0 - - - 0 1 1 1 1 1 6 0 0 0 - - - 0 1 1 1 1 1 Bit Values After a Reset 5 0 0 0 - - x 0 1 1 1 0 0 4 0 0 0 - - 0 0 1 1 1 0 0 3 0 0 0 0 0 0 0 1 0 0 1 1 2 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Locations ECH-EFH in set 1, bank 1, are not mapped. OSD character size control register OSD fade control register OSD row position control register OSD column position control register OSD background color control register On-screen display control register Halftone signal control register V-SYNC blank control register PWM2 data register PWM3 data register PWM4 data register PWM5 data register OSD color buffer CHACON FADECON ROWCON CLMCON COLCON DSPCON HTCON VSBCON PWM2 PWM3 PWM4 PWM5 COLBUF 240 241 242 243 244 245 246 252 248 249 250 251 247 F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH 0 0 0 0 0 0 0 - x x x x - 0 0 0 0 0 0 0 - x x x x - 0 0 0 0 0 0 0 - x x x x - 0 0 0 0 0 0 0 0 x x x x x 0 0 0 0 0 0 0 1 x x x x x 0 0 0 0 0 0 0 0 x x x x x 0 0 0 0 0 0 0 0 x x x x x 0 0 0 0 0 0 0 1 x x x x x Locations FDH-FFH in set 1, bank 1, are not mapped. Table 8-3. Page 1 Video RAM Register Values after a Reset Register Name Address 7 OSD video RAM 00H-FBH x 6 x Bit Values After a Reset 5 x 4 x 3 x 2 x 1 x 0 x 8-4 S3C880A/F880A nRESET and POWER-DOWN POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction Stop (opcode 7FH) however Stop available state must be set by value "10100101b" in "STCON" register before Stop instruction is invoked. If Stop instruction (opcode 7FH) is executed in Stop not available state (STCON = other value except "10100101b") CPU go to RESET address. After Stop instruction is executed the state return to Stop not available state. In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than maximum 10 A. All system functions stop when the clock "freezes," but data stored in the internal register file is retained. Stop mode can be released in one of two ways: by a nRESET signal or by an external interrupt. Using nRESET to Release Stop Mode Stop mode is released when the nRESET signal goes inactive (High level) from active (Low level) state. All system and peripheral control registers are reset to their default values and the contents of all data registers are retained. A reset operation automatically selects a slow clock (1/16) because CLKCON.3 and CLKCON.4 are cleared to '00B'. After the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the address stored in the ROM location 0100H. Using an External Interrupt to Release Stop Mode Two kinds of external interrupts with an RC-delay noise filter circuit can be used to release Stop mode. One external interrupts in the S3C880A/F880A interrupt structure that meet this requirement are INT0-INT3 (P1.0-P1.3) and the other one is V-sync input. Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller's current internal operating mode. Note that when Stop mode is released by an external interrupt, the current values in system and peripheral control registers are not changed. When you use an interrupt to release Stop mode, the CLKCON.3 and CLKCON.4 register values remain unchanged, and the currently selected clock value is used. If you use an external interrupt for Stop mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before entering Stop mode. The external interrupt is serviced when a Stop mode release occurs. Following the IRET from the service routine, the instruction immediately following the one that initiated Stop mode is executed. 8-5 nRESET and POWER-DOWN S3C880A/F880A IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, the CPU operations are halted while selected peripherals remain active. During Idle mode, the internal clock signal is gated off to the CPU and all peripherals except the OSD block timer A counter, PWM and capture (CAPA). Port pins retain the mode (input or output) they had at the time Idle mode was entered. There are two ways to release Idle mode: 1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of all data registers are retained. The reset automatically selects a slow clock (1/16) because CLKCON.3 and CLKCON.4 are cleared to '00B'. If interrupts are masked, a reset is the only way to release Idle mode. Activate any enabled interrupt, causing Idle mode to be released. When you use an interrupt to release Idle mode, the CLKCON.3 and CLKCON.4 register values remain unchanged, and the currently selected clock value is used. The interrupt is then serviced. When the return-from-interrupt (IRET) occurs, the instruction immediately following the one that initiated Idle mode is executed. NOTE Only external interrupts can be used to release Stop mode. To release Idle mode, you can use either type of interrupt (internal or external). 2. 200 k 0.1-10 F Internal Recommand External Circuit Figure 8-1. Reset Circuit Application 8-6 S3C880A/F880A nRESET and POWER-DOWN F PROGRAMMING TIP -- Enter to Stop Mode The following sample program shows you recommended entering Stop mode for the S3C880A/F880A. * * * ld STOP NOP NOP NOP * * * STCON, #10100101b ; After this instruction is executed ; Stop instruction is available ; NOP need more than three after STOP instruction STCON #10100101b STON Instruction Stop available state is released automatically after STOP instruction. Stop Available State Enable Disable Enable Stop State Disable Figure 8-2. Stop State Timing Diagram 8-7 nRESET and POWER-DOWN S3C880A/F880A F PROGRAMMING TIP -- Initial Settings for Address Space, Vectors, and Peripherals The following sample program shows you recommended initial settings for the S3C880A/F880A address space, interrupt vectors, and peripheral functions. Program comments guide you through the required steps: * * * OSD_REG OSD_FLG DSP_TYP VRAMAD WORK1 WORK2 REMOCON EQU EQU EQU EQU EQU EQU EQU * * * 0C8H 8 9 0CH 0BH 0AH 3FH ; OSD working register area ; General-purpose area ; General-purpose area ; CAPA data save register ORG DW ORG DW ORG DW DW DW DW DW ORG DW ORG DW ORG START DI LD LD CLR CLR SB1 02H CAPA_INT; 0BEH TIMERA_INT 0C0H P10_INT P11_INT OSD ROW_INT P12_INT P13_INT 0D4H V_SYNC_INT 0FCH TIMER0_INT 0100H Capture A interrupt ; Timer A interrupt ; ; ; ; ; P1.0 external interrupt P1.1 external interrupt OSD ROW interrupt P1.2 external interrupt P1.3 external interrupt ; V-sync interrupt ; Timer 0 interrupt BTCON,#0AAH CLKCON,#98H SYM SPL ; ; ; ; ; ; ; Disable all interrupts Disable the watchdog timer Non-divided clock Disable global and fast interrupts Stack pointer low byte "0" Stack area will start at 0FFH Select bank 1 (Continued on next page) 8-8 S3C880A/F880A nRESET and POWER-DOWN F PROGRAMMING TIP -- Initial Settings for Address Space, Vectors, and Peripherals (Continued) ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Enable OSD ROW interrupt Enable V-sync interrupt Disable OSD logic Select bank 0 Prescaler 4 Enable PWM counter Enable capture A interrupt Interrupt priority settings IRQ6 > 7 > 3 > 2 > 0 > 1 Enable level 2, 3, 6, and 7 interrupts Input mode Push-pull output mode Output mode Input mode Input mode Input mode Input mode Prescaler 6 Clock source CPU clock / 1000 Enable timer A interrupt Interval timer mode 4-millisecond interrupt LD LD SB0 LD HTCON,#2AH DSPCON,#0A0H PWMCON,#0E9H LD LD LD LD LD LD LD LD LD LD IPR,#0AEH IMR,#0CCH P0CONH,#00H P0CONL,#0FFH P1CONH,#0FFH P1CONL,#00H P2CONH,#00H P2CONL,#00H P3CONL,#00H TACON,#54H LD EI MAIN NOP NOP * * * TADATA,#03H NOP JP CAPA_INT: PUSH PUSH PUSH * * * T,MAIN ; Jump MAIN ; ; ; ; CAPA interrupt service Save page pointer to stack Save register pointer 0 to stack Save register pointer 1 to stack PP RP0 RP1 LD POP POP POP IRET REMOCON,CAPA RP1 RP0 PP ; ; ; ; ; REMOCON CAPA data Restore register pointer 1 value Restore register pointer 0 value Restore page pointer value Return from interrupt service routine (Continued on next page) 8-9 nRESET and POWER-DOWN S3C880A/F880A F PROGRAMMING TIP -- Initial Settings for Address Space, Vectors, and Peripherals (Continued) PUSH PUSH PUSH * * * TIMERA_INT PP RP0 RP1 ; TIMER_A interrupt service LD POP POP POP IRET V_SYNC_INT PUSH PUSH PUSH * * * TACON, #54H RP1 RP0 PP ; Clear pending bit ; Return from interrupt service routine PP RP0 RP1 ; V_SYNC interrupt service SB1 LD POP POP POP IRET OSD ROW_INT: PUSH PUSH PUSH * * * HTCON, #3AH RP1 RP0 PP ; Clear pending bit ; Return from interrupt service routine PP RP0 RP1 SB1 LD POP POP POP IRET P10_INT: P11_INT: P12_INT: P13_INT: TIMER0_INT: IRET HTCON, #2BH RP1 RP0 PP ; Clear pending bit ; P1.0 external interrupt ; P1.1 external interrupt ; P1.2 external interrupt ; P1.3 external interrupt ; Timer 0 interrupt ; Return from interrupt service routine 8-10 S3C880A/F880A I/O PORTS 9 OVERVIEW Port 0 I/O PORTS The S3C880A/F880A and the S3C880A/F880A microcontrollers have four I/O ports with a total of 26 pins. Up to 10 pins can be configured as n-channel open-drain outputs. Of these 10 open-drain pins, 6 pins can withstand loads of up to 6 volts and 4 pins can withstand loads of up to 5 volts. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required. Table 9-1 gives you a summary of port functions: Table 9-1. S3C880A/F880A Port Configuration Overview Configuration Options General I/O port, configurable for digital input or push-pull output. Pins P0.6-P0.7 are multiplexed to support alternative function. General I/O port, configurable for digital input or n-channel open-drain output. Pins 1.0-P1.5 can withstand up to 6-volt loads. Pins 1.0-P1.3 are multiplexed to support alternative functions. General I/O port, configurable for n-channel open-drain or push-pull output mode by software. Pins can withstand up to 5-volt loads. Each pin has an alternative function. General 2-bit I/O port, configurable for digital input or n-channel open-drain output. Pins can withstand up to 5 V. P3.0-P3.1 can be alternately used as external interrupt inputs ADC0-ADC1. Programmability Bit programmable 1 Bit programmable 2 Bit programmable 3 Bit programmable 9-1 I/O PORTS S3C880A/F880A PORT DATA REGISTERS Data registers for ports 0-3 have the structure shown in Figure 9-1. Table 9-2 gives you an overview of the port data register locations: Table 9-2. Port Data Register Summary Register Name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Mnemonic P0 P1 P2 P3 Decimal 224 225 226 227 Hex E0H E1H E2H E3H Location Set 1, bank 0 Set 1, bank 0 Set 1, bank 0 Set 1, bank 0 R/W R/W R/W R/W R/W I/O Port n Data Register (n = 0-3) MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Pn.7 Pn.6 Pn.5 Pn.4 Pn.3 Pn.2 Pn.1 Pn.0 Figure 9-1. Port Data Register Format Port 0 Port 0 is a bit-programmable general I/O port. Port 0 is accessed directly by writing or reading the port 0 data register, P0 (E0H, set 1, bank 0). The port 0 pins are configured by bit-pair settings in the P0CONH and P0CONL registers. P0CONH controls I/O for the upper byte pins and P0CONL controls I/O for the lower byte pins. 9-2 S3C880A/F880A I/O PORTS Port 0 Control Register, High Byte (P0CONH) E4H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P0.7/ADC2 P0.6/ADC2 P0.5 P0.4 P0CONH Pin Configuration Settings: 00 01 10 11 Input mode Input mode (P0.4-P0.5), ADC input mode (P0.6-P0.7) Push-pull output mode (P0.4-P0.5), open-drain output mode (P0.6-P0.7) Push-pull output mode (P0.4-P0.5), open-drain output mode (P0.6-P0.7) Figure 9-2. Port 0 High-Byte Control Register (P0CONH) Port 0 Control Register, Low Byte (P0CONL) E5H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P0.3 P0.2 P0.1 P0.0 P0CONL Pin Configuration Settings: 00 01 10 11 Input mode Input mode N-channel open-drain output mode (5V load capacity) Push-pull output mode Figure 9-3. Port 0 Low-Byte Control Register (P0CONL) 9-3 I/O PORTS S3C880A/F880A PORT 1 Port 1 is a bit-programmable general I/O port. Port 1 is accessed directly by writing or reading the port 1 data register, P1 (E1H, set 1, bank 0). The upper byte (P1.4-P1.7) and the lower byte (P1.0-P1.3) are controlled by the P1CONH and P1CONL registers, respectively. P1CONH is located at E6H in set 1, bank 0 and P1CONL is located at E7H in set 1, bank 0. Port 1 Control Register, High Byte (P1CONH) E6H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.7/T0CK P1.6 P1.5 P1.4 P1CONH Pin Configuration Settings: 00 01 10 11 Input mode Inputmode (P1.4-P1.6), Timer 0 clock input: T0CK (P1.7) P1.4-P1.5: N-channel open-drain mode (6V load capacity), P1.6-P1.7: Push-pull output mode P1.4-P1.5: N-channel open-drain mode (6V load capacity), P1.6-P1.7: Push-pull output mode Figure 9-4. Port 1 High-Byte Control Register (P1CONH) Port 1 Control Register, Low Byte (P1CONL) E7H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.3/INT3 P1.2/INT2 P1.1/INT1 P1.0/INT0 P1CONL Pin Configuration Settings: 00 01 10 11 Input mode: Interrupt disabled Input mode: Interrupt on rising edge Input mode: Interrupt on falling edge N-channel open-drain output mode (6V load capacity) Figure 9-5. Port 1 Low-Byte Control Register (P1CONL) 9-4 S3C880A/F880A I/O PORTS PORT 2 Port 2 is a bit-programmable general I/O port. Port 2 is accessed directly by writing or reading the port 2 data register, P2 (E2H, set 1, bank 0). The upper byte (P2.4-P2.7) and the lower byte (P2.0-P2.3) are controlled by the P2CONH and P2CONL registers, respectively. A reset clears the port 2 control registers to '00H', configuring the port 2 pins to normal input mode (P2.0-P2.3) and input mode (2.4-P2.7). You use P2CONH and P2CONL register settings to configure individual port 2 pins: Port 2 Control Register, High Byte (P2CONH) E8H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P2.7/OSDHT P2.6/T0 P2.5/PWM0 P2.4/PWM4 P2CONH Pin Configuration Settings: 00 01 10 11 Input mode N-channel open-drain output mode (5V load capacity) Push-pull output mode P2.4: PWM4 output mode (open-drain type) P2.5: PWM5 output mode (push-pull circuit type) P2.6: Timer 0 output mode (PWM or Interval; open-drain type) P2.7: OSD half-tone output mode (push-pull circuit type) Figure 9-6. Port 2 High-Byte Control Register (P2CONH) Port 2 Control Register, Low Byte (P2CONL) E9H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P2.3/PWM3 P2.2/PWM2 P2.1/PWM1 P2.0/PWM5 P2CONL Pin Configuration Settings: 00 01 10 11 Normal input mode N-channel open-drain output mode with 5V load capacity PWM output mode: N-channel open-drain type Push-pull output mode Figure 9-7. Port 2 Low-Byte Control Register (P2CONL) 9-5 I/O PORTS S3C880A/F880A PORT 3 Port 3 is a bit-programmable general I/O port. Only two bits are used. Port 3 is accessed directly by writing or reading the port 3 data register, P3 (E3H, set 1, bank 0). A reset operation sets the P3 data register to '00H', and the port 3 control register to `0FH', configuring the port 3 pins to output (open-drain) mode. Port 3 Control Register (P3CON) EBH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB No effect P3.1/ADC1 P3.0/ADC0 P3CON Pin Configuration Settings: 00 01 10 11 Input mode ADC input mode Input mode N-channel open-drain output mode (with 5V load capacity) Figure 9-8. Port 3 Control Register (P3CON) 9-6 S3C880A/F880A I/O PORTS F PROGRAMMING TIP -- Configuring I/O Port Pins to Specification The following sample program shows you how to configure the S3C880A/F880A I/O ports to specification. The following parameters are given for ports 0, 1, 2, and 3: -- Set P0.0 and P0.1 to input mode -- Set P0.2 and P0.3 to output mode -- Set P0.4 and P0.5 to input mode -- Set P0.6 and P0.7 to open-drain output mode -- Set P1.0-P1.1 to interrupt rising edge mode -- Set P1.2-1.5 to open-drain output mode -- Set P1.6- P1.7 to push-pull output mode -- Set P2.0 and P2.1 to open-drain output mode -- Set P2.2-P2.4 to input mode -- Set P2.6-2.7 to push-pull output mode -- Set P2.5 to PWM0 output mode -- Set P3.0-P3.1 to ADC input mode * * * SB0 LD LD P0CONH,#0F0H P0CONL,#0F0H ; Select bank 0 ; ; ; ; P0.4, P0.5 P0.6, P0.7 P0.0, P0.1 P0.2, P0.3 Input mode Open-drain output mode Input mode Output mode LD LD LD P1CONH,#0FFH P1CONL,#0F5H P2CONH,#0ACH ; P1.6-1.7 Push-pull output mode ; P1.2-1.5 Open-drain output mode ; P1.0, P1.1 Interrupt rising edge mode ; ; ; ; ; P2.4 Input mode P2.6, 2.7 Push-pull output mode P2.5 PWM0 output mode P2.0, P2.1 Open-drain output mode P2.2, P2.3 Input mode LD P2CONL,#05H LD * * * P3CONL,#05H ; P3.0, P3.1 ADC input mode 9-7 I/O PORTS S3C880A/F880A F PROGRAMMING TIP -- Clearing Port 0 Interrupt Pending Bits This sample program shows you how to clear the interrupt pending bits for port 1. The program parameters are as follows: -- Enable only the interrupt level 1 (IRQ1) for P1.0-P1.1 -- Set the interrupt priorities as P1.0 > P1.1 ORG VECTOR VECTOR * * * 0C0H EXT_INT_P10 EXT_INT_P11 nRESET ORG DI SB0 LD LD CLR * * * 0100H ; ; ; ; ; ; Disable all interrupts Select bank 0 Disable the watchdog timer Non-divided clock Stack pointer low byte "0" Stack area starts at 0FFH BTCON,#0AAH CLKCON,#98H SPL LD LD LD * * * IMR,#06H IPR,#11H P1CONL,#0AH ; Enable IRQ1 and IRQ2 interrupts ; IRQ1 > IRQ2 ; P1.0, P1.1 Input mode; falling edge interrupts SRP EI * * * #0C0H ; Set register pointer to 0C0H ; Enable interrupts MAIN NOP NOP * * * JP * * * T,MAIN (Continued on next page) 9-8 S3C880A/F880A I/O PORTS F PROGRAMMING TIP -- Clearing Port 1 Interrupt Pending Bits (Continued) ; ; ; ; P1.0 external interrupt service Save page pointer to stack Save register pointer 0 to stack Save register pointer 1 to stack EXT_INT_P10: PUSH PUSH PUSH * * * PP RP0 RP1 POP POP POP IRET EXT_INT_P11: PUSH PUSH PUSH * * * RP1 RP0 PP ; ; ; ; Restore register pointer 1 value Restore register pointer 0 value Restore page pointer value Return from interrupt service routine ; P1.1 external interrupt service PP RP0 RP1 POP POP POP IRET RP1 RP0 PP 9-9 I/O PORTS S3C880A/F880A NOTES 9-10 S3C880A/F880A BASIC TIMER and TIMER 0 10 BASIC TIMER and TIMER 0 MODULE OVERVIEW The S3C880A/F880A microcontrollers have two default timers: an 8-bit basic timer (BT) and an 8-bit general-purpose timer/counter, called timer 0 (T0). The basic timer (BT) has two alternative functions: 1) it can be used as a watchdog timer that provides an automatic reset mechanism in the event of a system malfunction, and 2) it can be used to signal the end of the required oscillation stabilization interval after a reset or a Stop mode release. The components of the basic timer are: -- Clock frequency divider (fOSC divided by 4096, 1024, or 128) with multiplexer -- 8-bit basic counter, BTCNT (set 1, bank 0, FDH, read-only) -- Basic timer control register, BTCON (set 1, D3H, read/write) -- Clock frequency divider (fOSC divided by 4096, 256, or 8) with multiplexer -- 8-bit counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA) -- Timer 0 match interrupt (T0INT) generation -- Timer 0 control register, T0CON (set 1, D2H, read/write) 10-1 BASIC TIMER and TIMER 0 S3C880A/F880A BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, clear the basic timer counter and frequency dividers, and enable or disable the watchdog timer function. It is located in set 1, address D3H, and is read/write addressable using Register addressing mode only. A reset clears BTCON to '00H'. This enables the watchdog function and selects a basic timer clock frequency of fOSC/4096. To disable the watchdog function, you must write the signature code '1010B' to the basic timer register control bits BTCON.7-BTCON.4. The 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH), can be cleared during the normal operation by writing a "1" to BTCON.1. To clear the frequency dividers for both the basic timer input clock and the timer 0 clock, you should write a "1" to BTCON.0. Basic Timer Control Register (BTCON) D3H, Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Watchdog timer enable bit: 1010B = Disable watchdog function Other value = Enable watchdog function Divider clear bit for basic timer and T0: 0 = No effect 1 = Clear divider Basic timer counter clear bit: 0 = No effect 1 = Clear basic timer counter Basic timer input clock selection bits: 00 = fosc/4096 01 = fosc/1024 10 = fosc/128 11 = fosc/16 Figure 10-1. Basic Timer Control Register (BTCON) 10-2 S3C880A/F880A BASIC TIMER and TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function The basic timer overflow signal can be programmed to generate a reset by setting the BTCON.7-BTCON.4 bits to any value other than '1010B'. (The '1010B' value disables the watchdog function.) A reset clears the BTCON register to '00H', automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the CLKCON register setting) divided by 4096 as the BT clock. With every overflow of the basic timer counter, a reset occurs. During the normal operation, this overflow-generated reset should be prevented from occurring. To do this, the basic timer counter value must be cleared by software (write BTCON.1 to "1") in regular intervals. If a system malfunction occurs due to circuit noise or some other error condition, the basic timer counter clear operation may not be executed and a basic timer overflow will occur, initiating a system reset. In other words, in normal operating condition the basic timer overflow loop (a bit 7 overflow of the 8-bit BT counter) is always broken by a clear counter instruction. An application program can use the basic timer as a watchdog timer to trigger an automatic system reset in case a malfunction occurs. Oscillation Stabilization Interval Timer Function The basic timer determines the oscillation stabilization interval after a reset or the release of Stop mode by an external interrupt. Whenever a reset or an external interrupt occurs during Stop mode, the oscillator begins operating. The basic timer value then starts increasing at the rate of fOSC/4096 (in the case of a reset), or at the rate of the preset clock source (in the case of an external interrupt). When bit 4 of the BT counter is set to "1", a signal is generated to indicate that the stabilization interval has elapsed. This allows the clock signal to be gated on to the CPU so that it can resume normal operation. In summary, the following events occur when Stop mode is released: 1. 2. 3. 4. During Stop mode a power-on reset or an external interrupt occurs to trigger a Stop mode release, and oscillation starts. If a power-on reset occurrs, the basic timer counter increases at the rate of fOSC/4096. If an external interrupt is used to release Stop mode, the basic timer value increases at the rate of the preset clock source. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows. When bit 4 of BTCNT is set to "1", the normal CPU operation resumes. 10-3 BASIC TIMER and TIMER 0 S3C880A/F880A Oscillation Stabilization Time Normal Operating mode 0.8 VDD VDD Reset Release Voltage RESET trst Internal Reset Release ~ RC 0.8 VDD Oscillator (XOUT) Oscillator Stabilization Time BTCNT clock BTCNT value 10000B 00000B tWAIT = (4096x16)/f OSC Basic timer increment and CPU operations are IDLE mode NOTE: Duration of the oscillator stabilization wait time, tWAIT, when it is released by a Power-on-reset is 4096 x 16/fOSC. tRST ~ RC (R is external resistor and C is on chip capacitor) Figure 10-2. Oscillation Stabilization Time on nRESET 10-4 S3C880A/F880A BASIC TIMER and TIMER 0 Normal Operating Mode VDD STOP Instruction Execution External Interrupt RESET STOP Release Signal STOP Mode Oscillation Stabilization Time Normal Operating Mode STOP Mode Release Signal Oscillator (XOUT) BTCNT clock 10000B BTCNT Value 00000B tWAIT Basic Timer Increment NOTE: Duration of the oscillator stabilzation wait time, tWAIT, it is released by an interrupt is determined by the setting in basic timer control register, BTCON. BTCON.3 0 0 1 1 BTCON.2 0 1 0 1 tWAIT (4096 x 16)/fosc (1024 x 16)/fosc (128 x 16)/fosc Invalid setting tWAIT (When fOSC is 8 MHz) 10.92 ms 2.7 ms 0.341 ms Figure 10-3. Oscillation Stabilization Time on STOP Mode Release 10-5 BASIC TIMER and TIMER 0 S3C880A/F880A TIMER 0 CONTROL REGISTER (T0CON) The timer 0 control register, T0CON, is used to select the timer 0 operating mode (interval timer) and input clock frequency, clear the timer 0 counter, and enable the T0 match interrupt. It also contains a pending bit for T0 match interrupt. It is located in set 1, address D2H, and is read/write addressable using register addressing mode. A reset clears T0CON to '00H'. This sets timer 0 to normal interval timer mode, selects an input clock frequency of fOSC/4096, and disables the T0 match interrupt. The T0 counter can be cleared at any time during the normal operation by writing a "1" to T0CON.3. To enable the T0 match interrupt (T0INT, IRQ0, vector FCH), you must set T0CON.1 to "1". The interrupt service routine must clear the pending condition by writing a "0" to the T0 interrupt pending bit, T0CON.0. Timer 0 Control Register (T0CON) D2H, Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB T0 input clock selection bits: 00 = fosc/4096 01 = fosc/256 10 = fosc/8 11 = External clock (T0CK) (Max fosc/8) T0 interrupt pending bit: 0 = No T0 interrupt pending 0 = Clear T0 pending bit (write) 1 = T0 interrupt is pending T0 interrupt enable bit: 0 = Disable T0 interrupt 1 = Enable T0 interrupt T0 operation mode selection bits: No effect 00 = Interval mode 01 = PWM mode 10 = PWM mode 11 = PWM mode T0 counter clear bit: 0 = No effect 1 = Clear the T0 counter (when write) Figure 10-4. Timer 0 Control Register (T0CON) 10-6 S3C880A/F880A BASIC TIMER and TIMER 0 TIMER 0 FUNCTION DESCRIPTION T0 Interrupts (IRQ0, Vector FCH) The T0 module can generate one interrupt: the timer 0 match interrupt (T0INT). T0INT is also in the level IRQ0, vector address: FCH. The T0INT pending condition must be cleared by software by writing a "0" to the T0CON.0 pending bit. Interval Timer Mode In interval timer mode, a match signal is generated when the counter value is identical to the value written to the T0 reference data register, T0DATA. The match signal generates a T0 match interrupt (T0INT, vector FCH) and then clears the counter. If, for example, you write the value '10H' to T0DATA, the counter will increment until it reaches '10H'. At this point, the T0 interrupt request is generated, the counter value is reset and counting resumes. IRQ0 (T0INT) Interrupt Enable/Disable PND T0CNT CLK Counter R (Clear) Comparator Match Data Register T0DATA Figure 10-5. Timer 0 Function Diagram (Interval Timer Mode) 10-7 BASIC TIMER and TIMER 0 S3C880A/F880A Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T0 pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the T0 data register. In PWM mode, however, the match signal does not clear the counter (it runs continuously, overflowing at 'FFH', and continuing incrementing from '00H'). Although it is possible to use the match signal to generate a T0INT interrupt, an interrupt is typically not used in PWM-type applications. Instead, the pulse at the T0 pin is held to Low level as long as the reference data value is less than or equal to the counter value; the pulse is then held to high level for as long as the data value is greater than the counter value. One pulse width is equal to tCLK x 256. (See figure 10-6) IRQ0 (T0INT) Interrupt Enable/Disable PND T0CNT CLK Counter Match Comparator CTL Data Register T0DATA NOTE: T0CON T0 pin High level when data > counter; Low level when data < counter = When timer 0 is configured to operate in PWM mode, interrupts are typically not used. Figure 10-6. Timer 0 Function Diagram (PWM Mode) 10-8 S3C880A/F880A BASIC TIMER and TIMER 0 Bit 1 nRESET or STOP Basic Timer Control Register (Write '1010xxxxB' to disable) Data Bus Bit 3, 2 1/4096 XIN DIV R Bit 0 R DIV 1/4096 1/256 1/8 T0CK 8-Bit Comparator MUX T0CNT 8-Bit Counter (Read-Only) Bits 7, 6 Data Bus 1/1024 1/128 MUX BTCNT 8-Bit Basic Counter (Read-Only) nRESET Overflow Bit 3 Bit 3 Interrupt Enable R Clear Match CTL Bits 4, 5 Bit 3 IRQ0 T0 (PWM & Interval) T0DATA Timer 0 Data Register (Read/Write) Basic Timer Counter Register Data Bus NOTE: Timer 0 Counter Register During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter is set to "1"). Figure 10-7. Basic Timer and Timer 0 Block Diagram 10-9 BASIC TIMER and TIMER 0 S3C880A/F880A F PROGRAMMING TIP -- Configuring the Basic Timer This example shows how to configure the basic timer to sample specifications: ORG nRESET DI SB0 LD LD CLR CLR * * * 0100H ; ; ; ; ; ; ; Disable all interrupts Select bank 0 Disable the watchdog timer Non-divided clock Disable global and fast interrupts Stack pointer low byte "0" Stack area starts at 0FFH BTCON,#0AAH CLKCON,#98H SYM SPL SRP EI * * * #0C0H ; Set register pointer 0C0H ; Enable interrupts MAIN LD BTCON,#52H ; Enable the watchdog timer ; Basic timer clock: fOSC/4096 ; Clear basic timer counter NOP NOP * * * JP * * * T,MAIN 10-10 S3C880A/F880A BASIC TIMER and TIMER 0 F PROGRAMMING TIP -- Configuring Timer 0 This sample program sets timer 0 to interval timer mode, determining the frequency of the oscillator clock, and the execution sequence which follows a timer 0 interrupt. The program givens are as follows: -- Timer 0 is used in interval mode; the timer interval is set to 4 milliseconds -- Oscillation frequency is 6 MHz -- General register 60H (page 0) 60H + 61H + 62H + 63H + 64H (page 0) is executed after a timer 0 interrupt ORG VECTOR ORG nRESET DI SB0 LD LD CLR CLR * * 0FCH T0INT 0100H ; Timer 0 interrupt (match) BTCON,#0AAH CLKCON,#98H SYM SPL ; ; ; ; ; ; ; Disable all interrupts Select bank 0 Disable the watchdog timer Non-divided clock Disable global and fast interrupts Stack pointer low byte "0" Stack area starts at 0FFH LD T0CON,#42H LD SRP EI * * T0DATA,#5DH #0C0H ; ; ; ; ; ; ; ; 01000010B Input clock is fOSC/256 Interval timer mode Enable the timer 0 interrupt Set timer interval to 4 milliseconds (6 MHz/256) / (93 + 1) = 0.25 kHz (4 ms) Set register pointer 0C0H Enable interrupts T0INT PUSH PUSH SB0 LD SRP0 INC ADD ADC ADC CP JR BITS PP RP0 PP,#00H #60H R0 R2,R0 R3,R2 R4,R0 R0,#32H ult,NO_200MS_SET R1.2 ; ; ; ; ; ; ; ; ; ; Save page pointer to the stack Save RP0 to stack Select bank 0 Page pointer 00H (select page 0) RP0 60H R0 R0 + 1 R2 R2 + R0 R3 R3 + R2 + Carry R4 R4 + R0 + Carry 50 x 4 = 200 ms ; Bit setting (61.2H) NO_200MS_SET: LD POP POP IRET T0CON,#42H RP0 PP ; ; ; ; Clear pending bit Restore register pointer 0 value Restore page pointer value Return from interrupt service routine 10-11 BASIC TIMER and TIMER 0 S3C880A/F880A NOTES 10-12 S3C880A/F880A TIMER A 11 OVERVIEW TIMER A The S3C880A/F880A microcontrollers have an 8-bit timer/counter (timer A). Each timer has a control register, an 8-bit counter register, an 8-bit data register, an 8-bit comparator. Timer A runs continuously. Counter register addresses are not mapped and they cannot, therefore, be read or written. TIMER CLOCK INPUT Timer A has different clock input options. You can select the non-divided CPU clock or the CPU clock divided by 1000. The selected clock input frequency for each timer can be scaled using the 4-bit prescaler that is located in bits 4-7 of the TACON register. TIMER A INTERRUPT CONTROL Timer A generate a match signal when the count value is equal to the referenced data value in the TADATA. When the interrupt enable bit is set for timer A, an interrupt is generated whenever a match is detected. The corresponding count register is then cleared and counting resumes. To enable the timer A interrupt, you should set TACON.2 to "1". The timer A interrupt pending bit is TACON.1. When a timer A pending bit read operation shows a "0" value, no interrupt is pending; when it is "1", an interrupt request is pending. When the request is acknowledged by the CPU and the service routine starts, the pending bit must be cleared by the interrupt service routine. To do this, you must write a "0" to the appropriate bit location. 11-1 TIMER A S3C880A/F880A TIMER A FUNCTION DESCRIPTION When a match occurs, the timer is reset to zero. TACON.3 TACON.1 TACON.2 1 + 1000 M U X 4-Bit Prescaler TA Counter 8-Bit Comparator 8-Bit TADATA Match R PND Timer A Interrupt (IRQ6,BEH) CPU CLK Figure 11-1. Timer A Block Diagram 11-2 S3C880A/F880A TIMER A TIMER A CONTROL REGISTER (TACON) The timer A control register, TACON, is located at F2H in set 1, bank 0. All bits are read/write addressable. The TACON register settings control four functions: -- Interrupt enable/disable -- Interrupt pending control (read for status, write to clear) -- Clock source selection -- Prescaler (4-bit) for timer clock input TACON.1 is the pending flag for the timer A interrupt (IRQ6, vector BEH). Application software can poll the TAIP bit to detect timer A interrupt requests. When an interrupt request is acknowledged, the interrupt service routine must clear TACON.1 by writing a "0" to the bit location. Note that there are two clock source selections for timer A: the CPU clock divided by 1000 or the non-divided CPU clock. A reset clears TACON to '00H', selecting the CPU clock/1000, and disabling the timer A interrupt. Timer A Control Register (TACON) F2H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB 4-bit prescaler for timer A clock 0000 0001 Divide input by 1 (non-divided) Divide input by 2 Not used Timer A interrupt pending bit: 0 = No interrupt pending (when read) 0 = Clear pending bit (when write) 1 = Interrupt is pending (when read) 1 = No effect (when write) Timer A interrupt enable: 0 = Disable interrupt 1 = Enable interrupt 1111 Divide input by 3-15 Timer A clock source selection bit: 0 = CPU clock divided by 1000 1 = Non-divided CPU clock Figure 11-2. Timer A Control Register (TACON) 11-3 TIMER A S3C880A/F880A F PROGRAMMING TIP -- Configuring Timer A This example sets timer A to normal interval mode, determining the oscillation frequency of the timer clock, the execution sequence that follows a timer A interrupt. The program parameters are: -- The timer interval is set to 10 milliseconds -- Oscillation frequency = 6 MHz -- General register 70H (page 0) 70H + 71H + 72H + 73H + 74H (page 0) is executed after a timer A interrupt ORG VECTOR ORG DI SB0 LD LD CLR CLR * * * 0BEH TAINT 0100H ; Timer A interrupt nRESET BTCON,#0AAH CLKCON,#98H SYM SPL ; ; ; ; ; ; ; Disable all interrupts Select bank 0 Disable the watchdog timer Non-divided clock Disable global and fast interrupts Stack pointer low byte "0" Stack area starts at 0FFH LD TACON,#54H LD SRP EI * * * TADATA,#59H #0C0H ; ; ; ; ; ; ; ; 01010100B PS 5 (divide-by-6) CPU clock/1000 Select interval mode for timer A 10-ms interval time (6 MHz/1000) / (59 + 1) = 100 Hz (10 ms) Set register pointer 0C0H Enable interrupts TAINT PUSH PUSH SB0 LD SRP0 INC ADD ADC ADC CP JR BITS PP RP0 PP,#00H #70H R0 R2,R0 R3,R2 R4,R0 R0,#64H ult,NO_1SEC_SET R1.2 ; ; ; ; ; ; ; ; ; ; Save page pointer to stack Save register pointer 0 to stack Select bank 0 Page pointer 00H (select page 0) RP0 70H R0 R0 + 1 R2 R2 + R0 R3 R3 + R2 + Carry R4 R4 + R0 + Carry 100 x 10 ms = 1000 ms (1 second) ; Bit setting (71.2H) (Continued on next page) 11-4 S3C880A/F880A TIMER A F PROGRAMMING TIP -- Configuring Timer A (Continued) NO_1SEC_SET: LD POP POP IRET TACON,#54H RP0 PP ; Clear pending bit ; Restore register pointer 0 value ; Restore page pointer value ; Return from interrupt service routine 11-5 TIMER A S3C880A/F880A NOTES 11-6 S3C880A/F880A PWM and CAPTURE 12 PWM AND CAPTURE PWM/CAPTURE MODULE The S3C880A/F880A microcontrollers have two 14-bit PWM circuits and four 8-bit PWM circuits. The 14-bit circuits are called PWM0 and PWM1; the 8-bit circuits are PWM2-PWM5. The operation of all the PWM circuits is controlled by a single control register, PWMCON. PWMCON also contains a 3-bit prescaler for adjusting the PWM frequency (cycle). The capture function, called capture A, is integrated in this block. Using PWMCON settings, you can enable the capture A interrupt and select the desired triggering edge for data capture on the CAPA input pin. The PWM counter is a 14-bit incrementing counter. It is used by the 14-bit PWM circuits. To start the counter and enable the PWM circuits, you must set PWMCON.5 to "1". If the counter is stopped, it retains its current count value; when re-started, it resumes counting from the retained count value. A 3-bit prescaler controls the clock input frequency to the PWM counter. By modifying the prescaler value, you can divide the input clock by one (non-divided), two, three, four, five, six, seven, or eight. The prescaler output is the clock frequency of the PWM counter. 12-1 PWM and CAPTURE S3C880A/F880A PWM CONTROL REGISTER (PWMCON) The control register for the PWM module, PWMCON, is located at the register address F8H in set 1, bank 0. Bit settings in the PWMCON register control the following functions: -- 3-bit prescaler for scaling the PWM counter clock -- Stop/start (or resume) the PWM counter operation -- Capture A interrupt enable and capture A edge selection A reset clears all PWMCON bits to logic zero, disabling the entire PWM module. PWM Control Register (PWMCON) F8H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB 3-bit prescaler for PWM counter clock: .4 .7 .6 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Non-divide Divide by 2 Divide by 3 Divide by 4 Divide by 5 Divide by 6 Divide by 7 Divide by 8 Capture function control bits: 00 = Disable capture function 01 = Capture on falling edges 10 = Capture on rising edges 11 = Capture on both edges Not used Capture interrupt enable bit: 0 = Disable capture interrupt 1 = Enable capture interrupt PWM counter enable bit: 0 = Stop counter 1 = Start (resume) counting Figure 12-1. PWM Control Register (PWMCON) 12-2 S3C880A/F880A PWM and CAPTURE PWM2-PWM5 The S3C880A/F880A microcontrollers have four 8-bit PWM circuits, called PWM2-PWM5. These 8-bit circuits have the following components: -- 14-bit counter with 3-bit prescaler -- 8-bit comparators -- 8-bit PWM data registers (PWM2-PWM5) -- PWM output pins (PWM2-PWM5) The PWM2-PWM5 circuits are controlled by the PWMCON register (F8H, set 1, bank 0). Data Bus 8 x4 8-bit PWM2-PWM5 Registers 8 x4 8-bit PWM2-PWM5 Comparators 8 CPU CLK PWMCON.5 PWMCON.1 3-bit P.S. Lower 8-bit of 14-bit Counter "1" When Reg > Count "0" When Reg < Count = PWM0/1 Logic Upper 6-bit of 14-bit Counter PWM2-PWM5 Output pins PWM2-PWM5 Output pins IRQ3 (02H) 2 6 PWMCON.3 Capture Register CAP Input 8 PWMCON.0 Data Bus Figure 12-2. Block Diagram for PWM2-PWM5 12-3 PWM and CAPTURE S3C880A/F880A PWM2-PWM5 FUNCTION DESCRIPTION All the four 8-bit PWM circuits function identically: each has its own 8-bit data register and 8-bit comparator. Each circuit compares a unique data register value to the lower 8-bit value of the 14-bit PWM counter. The PWM2-PWM5 data registers are located in set 1, bank 1, at locations F8H-FBH, respectively. These data registers are read/write addressable. By loading specific values into the respective data registers, you can modulate the pulse width at the corresponding PWM output pins, PWM2-PWM5. The level at the output pins toggles High and Low at a frequency equal to the counter clock, divided by 256 (28). The duty cycle of the PWM0 and PWM1 pins ranges from 0% to 99.6%, based on the corresponding data register values. To determine the PWM output duty cycle, its 8-bit comparator sends the output level High when the data register value is greater than the lower 8-bit count value. The output level is Low when the data register value is less than or equal to the lower 8-bit count value. The output level at the PWM2-PWM5 pins remains at Low level for the first 256 counter clocks. Then, each PWM waveform is repeated continuously, at the same frequency and duty cycle, until one of the following three events occurs: -- The counter is stopped -- The counter clock frequency is changed -- A new value is written to the PWM data register 12-4 S3C880A/F880A PWM and CAPTURE STAGGERED PWM OUTPUTS The PWM2-PWM5 outputs are staggered in order to reduce the overall noise level on the pulse width modulation circuits. If you load the same value to the PWM2-PWM5 data registers, a match condition (data register value is equal to the lower 8-bit count value) will occur on the same clock cycle for all the four 8-bit PWM circuits. The output of PWM3, PWM4, and PWM5 are delayed by one-half of a counter clock for subsequent clock cycles (see Figure 12-4). Counter Value (HEX) 0H Counter Clock (8 MHz) PWM = "0" 125 ns PWM = "1" 12.5 s PWMn = 80H 125 ns PWMn = FFH PWM Cycle 25 s 100H 200H 300H NOTES: 1. A counter clock value of 8 MHz is assumed for all timing values. 2. 'n' = 2-5, for PWM2-PWM5 Figure 12-3. PWM Waveforms for PWM2-PWM5 12-5 PWM and CAPTURE S3C880A/F880A 0H (After RESET) CPU Clock PWM2 100H PWM3 Match occurs; PWM2 toggles to high level PWM4 1/2-Clock Delay 1/2-Clock Delay PWM5 1/2-Clock Delay Figure 12-4. PWM Clock to PWM2-PWM5 Output Delays 12-6 S3C880A/F880A PWM and CAPTURE PWM0-PWM1 The S3C880A/F880A pulse width modulation (PWM) module has two 14-bit PWM circuits (PWM0 and PWM1). The 14-bit PWM circuits have the following components: -- 14-bit counter with 3-bit prescaler (an 8-bit counter with 6-bit extension is used for 14-bit output resolution) -- 8-bit comparator and extension cycle circuit -- 8-bit reference data registers (PWM0, PWM1) -- 6-bit extension data registers (PWM0EX, PWM1EX) -- PWM output pins (PWM0, PWM1) The PWM0 and PWM1 circuits are enabled by the PWMCON register (F8H, set 1, bank 0). PWM COUNTER The PWM counter is a 14-bit increasing counter comprised of a lower byte counter and an upper byte counter. To determine the PWM module's base operating frequency, the lower byte counter is compared to the PWM data register value. In order to achieve higher resolutions, the lower six bits of the upper byte counter can be used to modulate the "stretch" cycle. To control the "stretching" of the PWM output duty cycle at specific intervals, the 6-bit extended counter value is compared with the 6-bit value (bits 2-7) that you write to the module's extension register. PWM DATA AND EXTENSION REGISTERS Two PWM (duty) data registers, located in set 1, bank 0, determine the output value generated by each 14-bit PWM circuit. PWM0 and PWM1 are read/write addressable. -- 8-bit data registers PWM0 (F4H) and PWM1(F6H) -- 6-bit extension registers PWM0EX (F5H) and PWM1EX (F7H) of which only bits 2-7 are used To program the required PWM output, you should load the appropriate initialization values into the 8-bit data registers (PWM0, PWM1) and the 6-bit extension registers (PWM0EX, PWM1EX). To start the PWM counter, or to resume counting, you should set PWMCON.5 to "1". A reset operation disables all PWM output. The current counter value is retained when the counter stops. When the counter starts, counting resumes at the retained value. PWM CLOCK RATE The timing characteristics of both 14-bit output channels are identical, and are based on the maximum 8-MHz CPU clock frequency. The 2-bit prescaler value in the PWMCON register determines the frequency of the counter clock. You can set PWMCON.6 and PWMCON.7 to divide the CPU clock frequency by 1 (non-divided), 2, 3, 4, 5, 6, 7, or 8. Because the maximum CPU clock rate for the S3C880A/F880A microcontrollers is 8 MHz, the maximum base PWM frequency is 31.25 kHz (8 MHz divided by 256). This assumes a non-divided CPU clock. 12-7 PWM and CAPTURE S3C880A/F880A Table 12-1. PWM0 and PWM1 Control and Data Registers Register Name PWM0 data registers Mnemonic PWM0 PWM0EX PWM1 data registers PWM1 PWM1EX PWM control register PWMCON Address (Set 1, Bank 0) F4H F5H F6H F7H F8H Function 8-bit PWM0 basic cycle frame value 6-bit extension ("stretch") value 8-bit PWM1 basic cycle frame value 6-bit extension ("stretch") value PWM0 counter stop/start (resume), and 3-bit prescaler for CPU clock; also contains capture A control settings PWM0 AND PWM1 FUNCTION DESCRIPTION The PWM output signal toggles to Low level whenever the lower 8-bit counter matches the reference value stored in the module's data register (PWM0, PWM1). If the value in the PWM data register is not zero, an overflow of the lower counter causes the PWM output to toggle to High level. In this way, the reference value written to the data register determines the module's base duty cycle. The value in the 6-bit extension counter (the lower six bits of the upper counter) is compared with the extension settings in the 6-bit extension data register (PWM0EX, PWM1EX). This 6-bit extension counter value (bits 2-7), together with extension logic and the PWM module's extension register, is then used to "stretch" the duty cycle of the PWM output. The "stretch" value is one extra clock period at specific intervals, or cycles (see Table 12-2). If, for example, the value in the extension register is '1', the 32nd cycle will be one pulse longer than the other 63 cycles. If the base duty cycle is 50%, the duty of the 32nd cycle will therefore be "stretched" to approximately 51% duty. For example, if you write 80H to the extension register, all odd-numbered pulses will be one cycle longer. If you write FCH to the extension register, all pulses will be stretched by one cycle except the 64th pulse. PWM output goes to an output buffer and then to the corresponding PWM0 and PWM1 output pin. In this way, you can obtain high output resolution at high frequencies. Table 12-2. PWM Output "Stretch" Values for Extension Registers PWM0EX and PWM1EX PWM0EX/PWM1EX Bit 7 6 5 4 3 2 1 0 "Stretched" Cycle Number 1, 3, 5, 7, 9, ..., 55, 57, 59, 61, 63 2, 6, 10, 14, ..., 50, 54, 58, 62 4, 12, 20, ..., 44, 52, 60 8, 24, 40, 56 16, 48 32 Not used Not used 12-8 S3C880A/F880A PWM and CAPTURE 8-bit PWM2-PWM5 Registers 8 "1" When Reg > Count "0" When Reg < Count Match when Reg = Count PWM0,PWM1 Output pins 8-bit PWM2-PWM5 Comparators CPU CLK 8 3-bit P.S. PWMCON.5 Lower 8-bit of 14-bit Counter Upper 6-bit of 14-bit Counter Extension Logic 1, 3, ..., 61, 63 Bit 7 6-bit Extension Registers (PWM0EX, PWM1EX) Bit2 32 Figure 12-5. Block Diagram for PWM0 and PWM1 12-9 PWM and CAPTURE S3C880A/F880A F PROGRAMMING TIP -- Programming PWM0 to Sample Specifications This example shows how to program the 14-bit pulse-width modulation module, PWM0. The program parameters are as follows: -- The oscillation frequency of the main crystal is 6 MHz -- PWM0 data is in the working register R0 -- PWM0EX (PWM0 extension value) is in the working register R1, bits 2-7 The program performs the following operations: 1. 2. 3. Set the PWM0 frequency to 23.437 kHz If R3.0 = "1", then PWM PWM + 12H (If an overflow occurs from R0, then R0 0FFH and R1 0FCH.) If R3.0 = "0", then PWM PWM - 11H (If an underflow occurs from R0, then R0 00H and R1 00H.) PWMCON N (0) R3.0 = 1? #20H PWM Control Register Setting Y (1) R1 N R1 - #20H Underflow? R1 Y Y R1 R1 + #48H Carry? Y R1 - #20H Borrow? N R0 R1 + #01H Carry? N R0 R1 Y Max. value Max. value R0 R1 Min. value Min. value N PWM0EX PWM0 R1 R0 Figure 12-6. Decision Flowchart for PWM0 Programming Tip 12-10 S3C880A/F880A PWM and CAPTURE F PROGRAMMING TIP -- Programming PWM0 to Sample Specifications (Continued) * * * LD * * * PWMCON,#20H ; PS 0 (Select 23.437-kHz PWM frequency) ; Enable the PWM counter BTJRF pwm0_inc: ADD JR INC JR LD LD JR pwm0_dec: SUB JP SUB JR CLR CLR pwm0_data_end: LD LD * * * pwm0_dec,R3.0 ; If R3.0 = "0", then jump to pwm0_dec R1,#48H NC,pwm0_data_end R0 NZ,pwm0_data_end R0,#0FFH R1,#0FCH T,pwm0_data_end ; ; ; ; ; ; ; If R3.0 = "1", then add 48H to the PWM data If no carry, go to pwm0_data_end R0 R0 + 1 If no overflow, jump to pwm0_data_end for update If overflow, set 0FFH to R0 Set 0FCH to R1 Jump to pwm0_data_end unconditionally R1,#44H NC,pwm0_data_end R0,#01H NC,pwm0_data_end R0 R1 ; ; ; ; ; ; R3.0 = "0", so subtract 44H from PWM data If no borrow, jump to pwm0_data_end for update Decrement R0 (R0 R0 - 1) If no borrow, jump to pwm0_data_end Clear data R0 Clear data R1 PWM0EX,R1 PWM0,R0 ; Load new value to PWM0EX (bits 2-7) ; Load new value to PWM0 12-11 PWM and CAPTURE S3C880A/F880A CAPTURE UNIT An 8-bit capture unit is integrated in the PWM module. The capture unit detects incoming signal edges and can be used to measure the pulse width of the incoming signals. PWMCON register settings control the capture unit, which has the following components: -- 8-bit capture data register (CAPA) -- Capture input pin (CAPA/Pin 36) -- 8-bit capture interrupt (IRQ3, vector 02H) The capture unit captures the upper 8-bit value of the 14-bit counter when a signal edge transition is detected at the CAPA pin. The captured value is then dumped into the capture A data register, also called CAPA, where it can be read. Using PWMCON.0 and PWMCON.1 settings, you can set edge detection at the CAPA pin for rising edges, falling edges, or for both signal edge types. You can also use signal edges at the CAPA pin to generate an interrupt. PWMCON.3 is the capture A interrupt enable bit. The capture interrupt is in the level 3 (IRQ3) and its vector address is 02H. Using the capture A interrupt, you can read the contents of the CAPA data register from edge to edge and use the values to calculate the elapsed time between pulses. CPU CLK 3-bit P.S. PWMCON.5 PWMCON.1 Lower 8-bit of 14-bit Counter Upper 6-bit of 14-bit Counter IRQ3 (02H) 2 6 PWMCON.3 Capture Register CAP Input 8 PWMCON.0 Data Bus Figure 12-7. Block Diagram for Capture A 12-12 S3C880A/F880A PWM and CAPTURE F PROGRAMMING TIP -- Programming the Capture Module to Sample Specifications This example shows you how to program the S3C880A/F880A capture A module. The sample parameters are as follows: -- The main oscillator frequency is 6 MHz -- Timer A interrupt occurs every 2 ms -- The following waveform is currently being input at the capture (CAPA) pin: tL tH -- The following registers are assigned for program values: Register 70H Register 71H Register 72H Register 73H Register 74H Register 77H DWNCNT CAPCNT FLAG LDR ; First captured count value ; Second captured count value ; Third captured count value ; Down-counter; decremented by 1 with each timer A interrupt ; Capture counter ; Flags Here is some additional information about the sample program: 1. 2. If 4.35 ms < tH, tL < 4.6 ms, then set bit zero (LDR) in the register 77H; otherwise clear the zero bit (LDR) in the register 77H. If the interval between two rising signal edges (capture trigger) is > 30 ms, disregard the capture setting. Figures 12-4 and 12-5 show decision flowcharts for the sample program. 12-13 PWM and CAPTURE S3C880A/F880A Main Routine Timer A Interrupt Timer A Setting Capture Unit Setting Y (zero) Flag CAPA 0 Rising Enable DWNCNT = 0? Y (zero) Back up the PP, PR0 DWNCNT = 0? N (not zero) N (not zero) DWNCNT Main JOB Other JOB DWNCNT - #1H Restore PP, RP0 RET Figure 12-8. Decision Flowchart (Main Routine and Timer A Interrupt) 12-14 S3C880A/F880A PWM and CAPTURE Capture A Interrupt Save PP, RP0 CAPCNT "1" Y (#01) R1 CAPCNT = #02? Y (#02) R2 3rd capture N CAPCNT + 1 "0" Flag = 0? CAPCNT = #01? 2nd capture Flag DWNCNT CAPCNT "1" #0FH #00H R0 CAPA 1st capture Interrupt on both edges SUB R2, R1 SUB R1, R0 4.35 ms < R1 R2 < 4.6 ms Y N LDR LDR "1" CAPA "0" Disable Restore PP, RP0 RET Figure 12-9. Decision Flowchart for Capture A Interrupt 12-15 PWM and CAPTURE S3C880A/F880A F PROGRAMMING TIP -- Programming the Capture Module to Sample Specifications * * * LDR DWNCNT CAPCNT FLAG EQU EQU EQU EQU * * * 0 3 4 7 CLR LD LD * * * PP TACON,#54H TADATA,#01H ; ; ; ; Select page 0 PS 5, interval mode Enable timer A interrupt 2-ms interval (6 MHz /1000 / 6 / 2 = 0.5 kHz = 2 ms) EXEC_MAIN: SRP0 CP JP BITR LD MAIN: * * * #70H RDWNCNT,#00H NE,MAIN R7.FLAG PWMCON,#0AH ; ; ; ; ; ; ; RP0 70H Down-counter = "0"? If not zero, then jump to MAIN Clear the 'FLAG' Enable capture A interrupt Trigger interrupt on rising edges Other job... JP * * * T,exec_main ; For looping TAINT PUSH PUSH SRP0 CP JP DEC * * * PP RP0 #70H RDWNCNT,#00H EQ,ta_exec RDWNCNT ; ; ; ; ; ; Save page pointer Save register pointer 0 RP0 70H R3 (down-counter) = "0"? If not zero, then decrement R3 by 1 TA_EXEC: POP POP IRET RP0 PP ; Restore register pointer 0 ; Restore page pointer ; Return from timer A interrupt service routine (Continued on next page) 12-16 S3C880A/F880A PWM and CAPTURE F PROGRAMMING TIP -- Programming the Capture Module to Sample Specifications (Continued) CAPINT PUSH PUSH SRP0 INC BTJRT BITS CLR LD LD LD PP RP0 #70H RCAPCNT cap_one,R7.FLAG R7.FLAG RCAPCNT RDWNCNT,#0FH R0,CAPA PWMCON,#0BH ; ; ; ; ; ; ; ; ; ; ; ; Save the page pointer to stack Save register pointer 0 to stack RP0 70H Increment the capture counter R7.FLAG "1", then jump to cap_one Set R7.FLAG Clear capture counter Down-counter 15 (for counting 30 ms) R0 1st captured count value CAPA = 0F9H, page 0 Enable capture interrupt Trigger interrupt on both rising and falling edges CAP_END POP POP IRET CP JP LD JR RP0 PP ; Restore the register pointer 0 value ; Restore the page pointer value ; ; CAPCNT = #01H? ; ; R1 2nd captured count value ; ; CAPCNT = #02H? ; ; Clear the LDR bit in R7 ; Disable the capture module ; CAP_ONE RCAPCNT,#01H NE,cap_con2 R1,CAPA T,cap_end RCAPCNT,#02H EQ,cap_con3 R7.LDR PWMCON,#00H T,cap_end CAP_CON2 CP JP CAP_CON4 BITR CAP_CON5 LD JR (Continued on next page) 12-17 PWM and CAPTURE S3C880A/F880A F PROGRAMMING TIP -- Programming the Capture Module to Sample Specifications (Concluded) CAP_CON3 LD SUB SUB CP JP CP JP CP JP CP JP BITS JP * * * R2,CAPA R2,R1 R1,R0 R1,#24H UGT,cap_con4 R2,#24H UGT,cap_con4 R1,#22H ULT,cap_con4 R2,#22H ULT,cap_con4 R7.LDR T,cap_con5 ; ; ; ; R2 R2 R1 24H = 3rd capture count value (3rd capture value - 2nd capture value) (2nd capture value - 1st capture value) 4.6 ms ; If High signal period > 4.6 ms, then go to cap_con4 ; ; If Low signal period > 4.6 ms, then go to cap_con4 ; 22H = 4.35 ms ; If High signal period < 4.35 ms, then go to cap_con4 ; ; If Low signal period < 4.35 ms, then go to cap_con4 ; Set bit 'LDR' ; Jump to cap_con5 unconditionally 12-18 S3C880A/F880A ON-SCREEN DISPLAY 13 OVERVIEW ON-SCREEN DISPLAY (OSD) The on-screen display (OSD) module displays channel number, the time, and other information on a display screen. The OSD character display module has 252 locations and supports a set of maximum 1024 characters. (Two characters are reserved: 00H for the blank function and 01H for the test pattern.) There are sixty four display colors. PATTERN GENERATION SOFTWARE For application development using the S3C880A/F880A microcontrollers, Samsung provides OSD pattern generation software (OSDFONT.exe). You can customize standard OSD patterns contained in this file. Table 13-1. OSD Function Block Summary OSD Function Block Video RAM (note) Function Description Located in register page 1, the video RAM contains 252 "word" lines. Each line is 14 bits long. Each 14-bit RAM address stores an 10-bit character code, a character halftone or character background color display control bit, and a 3-bit color code. Video RAM locations can be read or written: 00H-BFH can be accessed using any addressing mode; C0H-FBH can be accessed using Indirect Register or Indexed addressing mode only. The character ROM contains an 18-dot x 16-dot matrix data for 1024 characters. It is synchronized with the internal dot clock. The ROM outputs the dot matrix data for each character. The function of two characters is pre-determined: 00H is used for blank (no-display) data and 01H is for a factory test pattern. Output control logic receives input from the Character ROM, OSD control registers, and fade control circuits. It then decides what to display on the screen and what color the display should be. On the basis of truth table calculations, the final OSD signals (blue, green, red, blank, and H/T) are output from the OSD block at pins 22-25, 21. Character ROM Output control logic NOTE: The video RAM can be cleared only by "LD" instruction. 13-1 ON-SCREEN DISPLAY S3C880A/F880A INTERNAL OSD CLOCK Red-green-blue (RGB) color outputs, as well as display rates and positions, are determined by the clock signal, DOT_CLK. This signal is generated by the L-C oscillator and is scaled by the dot and column counter. DOT_CLK equals the OSD oscillator clock divided by the clock divider value. The clock divider value is set by the horizontal character size settings in the CHACON register. The rate at which each new display line is generated is determined by H-sync input. The rate at which each new frame (screen) is generated is determined by V-sync input. For stable on screen display operation, the CPU clock frequency should faster than OSD clock. OSD VIDEO RAM The OSD video RAM contains 252 word lines. Each line is 14 bits long. Of these 14 bits, eight are character display codes (bits 0-9). Bit 13 is the character halftone or character background color display control bit and bits 10-12 are used to determine the red, green, and blue components of the character color. 13-2 S3C880A/F880A ON-SCREEN DISPLAY Register Data Bus Register Address Bus fOSD Column Address (5) XOR Dot and Column Counter XOR ROW interrupt (IRQ2, 0C4H) ROWINT Character Color (3) Line and Row Counter Character Generator ROM (1024 x 18 x 16) Halfone (1) Row Address (4) Video RAM (252 x 14 Bits) Color Buffer (5) H-SYNC Polarity Selector V-SYNC CHAR CODE (10) Line Address (5) Line Count (6) Character Out (16-Dot) Dot Clock Output Control Logic Red Green Blue Blank Halftone Figure 13-1. On-Screen Display Function Block Diagram 13-3 ON-SCREEN DISPLAY S3C880A/F880A Data Bus 6-Bit 00H = Row 0, Column 0 01H = Row 0, Column 1 FBH = Row 11, Column 20 Bit 3 Color Buffer (FCH), Bits 0-5 H/T and BGRND Bit 2 R Bit 1 G Bit 0 B Bit 4-5 VRAM Data Bus 8-Bit LSB(Bit 0) Color Code H/T and BGRND H/T and BGRND H/T and BGRND H/T and BGRND VRAM (Bit8-9) MSB(Bit 9) B B B B Row 0, Column 0 Row 0, Column 1 Row 0, Column 2 Row 0, Column 3 R R R R G G G G Character Code (10-Bit) Character Code (10-Bit) Character Code (10-Bit) Character Code (10-Bit) ~ Row 11, Column 18 Row 11, Column 19 Row 11, Column 20 H/T and BGRND H/T and BGRND H/T and BGRND R R R G G G B B B Character Code (10-Bit) Character Code (10-Bit) Character Code (10-Bit) 10-Bit 14-Bit ~ Figure 13-2. On-Screen Display Video RAM Data Organization 13-4 S3C880A/F880A ON-SCREEN DISPLAY OSD CONTROL REGISTER OVERVIEW Seven control registers are used to control specific functions of the on-screen display module: There are seven control registers for OSD functions and one color buffer register: DSPCON CHACON FADECON ROWCON CLMCON COLCON HTCON COLBUF VSBCON OSDFRG1/2 OSDSMH1/2 OSDCOL OSDFLD OSDPLTR1/2 OSDPLTG1/2 OSDPLTB1/2 Display control register Character size and fade control register Fade control register Row display position and inter-row spacing control register Column display position and inter-column spacing control register Background color control register Halftone signal control register Character color buffer register V-sync blank time control register Fringe or border control registers Smooth display control registers OSD factor control register Field control register Palette color mode Red 1/2 Palette color mode Green 1/2 Palette color mode Blue 1/2 These registers are described in this section within the context of the OSD hardware module description. For detailed quick-reference descriptions of the control register bit settings, please refer to Section 4, "Control Registers." 13-5 ON-SCREEN DISPLAY S3C880A/F880A DISPLAY CONTROL REGISTER (DSPCON) Settings in the display control register, DSPCON (F5H, set 1, bank 1), are used to enable and disable the on-screen display to select halftone or background color for character displays, choose the polarity for H-sync and V-sync signal synchronization, and as OSD ROW counter which is read-only (bit4-bit7). Display Control Register (DSPCON) F5H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB OSD Row counter (Read-only) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Row0 Row1 Row2 Row3 Row4 Row5 Row6 Row7 Row8 Row9 Row10 Row11 Display enable bit: 0 = Disable OSD (turn off L-C osc) 1 = Enable OSD (turn on L-C osc) Halftone or background color selection bits (for character data in bit 13 of video RAM): 00 = Character background color 01 = Not used 10 = Halftone output 11 = Character halftone and background color 1100-1111: Not used Clock edge selection for H/V-sync polarity: 0 = Rising edges 1 = Falling edges Figure 13-3. OSD Display Control Register (DSPCON) NOTE Refer to the PROGRAMMING TIP - Row Interrupt Function of 13-24. 13-6 S3C880A/F880A ON-SCREEN DISPLAY OSD Enable/Disable The DSPCON.0 setting enables or disables the on-screen display module. To enable the OSD (turn L-C oscillation on), set DSPCON.0 to "1"; to disable OSD (turn L-C oscillation off), clear DSPCON.0 to "0". When you do not use the display module, we recommend that you keep DSPCON.0 cleared to "0" in order to reduce possible noise generation by the L-C oscillator. The DSPCON.0 settings determine the on/off condition of L-C oscillation, synchronized with Vsync input. And the OSD output can be turned on or off in OSD row units when L-C oscillation is on. At the point the value of DSPCON.0 is changed from "1" to "0" in the middle of a frame, OSD is disabled (OSD output is off). In this condition, L-C oscillation becomes off at the next Vsync input. When the value is shifted from "0" to "1", OSD is enabled (OSD output is on) and L-C oscillation returns to "on" at the following Vsync input. H-Sync and V-Sync Polarity Selection DSPCON.3 selects the triggering edge of H-sync and V-sync inputs to the OSD block. Incoming sync pulses enter a polarity option circuit that is controlled by the SYNC bit. If DSPCON.3 = "0", rising edges are selected; if it is "1", falling edges are selected. Character Halftone or Character Background Color Selection DSPCON.2 and DSPCON.1 let you select a halftone or background color display for individual characters. (Which characters are displayed as halftones, or with character background color, or with character halftone, or with character background color, or with character halftone and background color, depends on the bit 13 settings in the character video RAM data) When DSPCON.2-.1 = "00", the character background color option is selected; when DSPCON.2-.1 = "10", the character halftone function is selected; when DSPCON.2-.1 = "11", the character halftone and background color option are selected; but DSPCON.2-.1 = "01" is not used. ROW Counter Function DSPCON.4-DSPCON.7 to the OSD ROW read data. OSD ROW counter indicates the OSD ROW currently displayed. One ROW comprises one character (18 lines) and inter-ROW space (ROWCON.2-.0). The Row counter value for the first ROW after a Vsync input is set to "0". 13-7 ON-SCREEN DISPLAY S3C880A/F880A CHARACTER SIZE CONTROL REGISTER (CHACON) Using the character size control register, CHACON, you can specify four different standard character sizes in both vertical and horizontal directions. You also use the CHACON register to select rows (0-11) for the character fade function (see Figure 13-5). Vertical character size is defined by bits 6 and 7 of the CHACON register; horizontal direction is defined by bits 4 and 5. There are four basic character size settings: x1, x2, x3, and x4. Size 'x1' is the smallest and 'x4' is the largest. For example, to display a 'x1' (horizontal) by 'x1' (vertical) size character, you should clear CHACON.4- CHACON.7 to "0". To display a 'x4' by 'x4' size character, you should set bits 4-7 to '1111B'. You can also combine different vertical and horizontal size selections to produce flattened or elongated characters (see Figure 13-5). "1 dot" is a minimum unit of character size. 1 character is composed of 16 dots in width and 18 dots in length. 1 dot in width is 1 fosd clock and 1 dot in length is 1 H-sync line. 1 dot of 1x1 character size (minimum unit) is composed of 1 fosd clock and 2 H-sync line (even + odd field). Character size in width is increased by 1 clock. So x1, x2, x3, and x4 in width are the same as 1, 2, 3 and 4 clock, respectively. Character size in length is increased by 2 H-sync line (even field + odd field), so x1 and x2 in length are the same as 2 H-sync line (even field + odd field) and 4 H- sync line (even field + odd field + even field + odd field), respectively. Half dot in width is 1/2 fosd clock, and 1/2 dot in length is 1 H-sync line (even or odd field). In the fringe and boarder function, 1/2 dot setting can be used. So, please be more careful in using the 1/2 dot to prevent the blink. (Because the character size is changed in 1 dot unit or set to 1/2 dot in fringing or boarder function, blinking can occur in interlace scan, so care must be taken when 1/2 dot is used for width.) OSD Character Size Control Register (CHACON) F0H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Vertical character size selection bits: 00 = 'x1' size 01 = 'x2' size 10 = 'x3' size 11 = 'x4' size Horizontal character size selection bits: 00 = 'x1' size 01 = 'x2' size 10 = 'x3' size 11 = 'x4' size Fade row address selection bits: 0000 = Row 0 0110 = Row 6 0001 = Row 1 0111 = Row 7 0010 = Row 2 1000 = Row 8 0011 = Row 3 1001 = Row 9 0100 = Row 4 1010 = Row 10 0101 = Row 5 1011 = Row 11 Figure 13-4. OSD Character Size Control Register (CHACON) 13-8 S3C880A/F880A ON-SCREEN DISPLAY Horizontal = x2 Vertical = x2 Horizontal = x3 Vertical = x3 Horizontal = x4 Vertical = x4 Horizontal = x1 Vertical = x1 Horizontal = x3 Vertical = x2 Horizontal = x2 Vertical = x3 Figure 13-5. OSD Character Sizing Dimensions 13-9 ON-SCREEN DISPLAY S3C880A/F880A FADE-IN AND FADE-OUT CONTROL REGISTER (FADECON) The OSD block lets you program fade-in and fade-out displays. A fade-in display is one in which a character matrix is displayed incrementally until the complete character "appears". A fade-out display shows the complete character matrix first and then decrements the matrix line-by-line until the character "disappears" from the display field. The address of the character display (and the specific line) to be faded-in or faded-out is selected by writing bit values into the CHACON and FADECON registers. Bits 3-0 in the CHACON register specify the 4-bit video RAM address of one of the twelve rows (0-11) of the fade display. Bits 0-4 in the FADECON register specify the 5-bit line address within the selected row. Fade direction is controlled by FADECON.5. There are two choices of fade direction: before (FADECON.5 = "0") and after (FADECON.5 = "1"). When you select fade before, the character matrix is faded starting with line 0. When you select fade after, the matrix is faded starting with inter-row space line 6. (The inter = row space line 6 start position is only a suggestion, however, as the fade interval is assignable by software.) To enable the fade function, you should set FADECON.6 to "1". (FADECON.7 is not used). NOTE To avoid confusion in determining fade row and line addresses in the CHACON and FADECON registers, please note that line is a horizontal value that encompasses the entire character display field while row is a horizontal value for the character display matrix. OSD Fade Control Register (FADECON) F1H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used Fade function enable bit: 0 = Fade disable 1 = Fade enable Fade row address selection bits: 00000 = Line 0 00001 = Line 1 00010 = Line 2 00011 = Line 3 00100 = Line 4 00101 = Line 5 00110 = Line 6 00111 = Line 7 Fade direction selection bit: 01000 = Line 8 01001 = Line 9 0 = Fade before matrix 01010 = Line 10 01011 = Line 11 1 = Fade after matrix 01100 = Line 12 01101 = Line 13 01110 = Line 14 01111 = Line 15 10000 = Line 16 10001 = Line 17 10010 = Inter-row space Line 0 (1H) 10011 = Inter-row space Line 1 (2H) 10100 = Inter-row space Line 2 (3H) 10101 = Inter-row space Line 3 (4H) 10110 = Inter-row space Line 4 (5H) 10111 = Inter-row space Line 5 (6H) 11000 = Inter-row space Line 6 (7H) 11001-11111 = Not used Figure 13-6. OSD Fade Control Register (FADECON) 13-10 S3C880A/F880A ON-SCREEN DISPLAY ROW n-1 n n+1 Line 12 13 14 15 16 17 18 (Inter-row space Line 0) 19 (Inter-row space Line 1) 20 (Inter-row space Line 2) 21 (Inter-row space Line 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 (Inter-row space Line 0) 19 (Inter-row space Line 1) 20 (Inter-row space Line 2) 21 (Inter-row space Line 3) 0 1 2 3 4 5 6 7 Figure 13-7. Line and Row Addressing Conventions when ROWCON.2-.0 = "100" 13-11 ON-SCREEN DISPLAY S3C880A/F880A COLUMNS 0-20 ROWS 0-11 P M J G Q N K H DE AB Line = 0 Line = 12 Fade After (Fade Line = 13, Fade Line = No Display) CHACON FADECON 05H (Fade Row = 5) 6DH (Fade Line = 13; Fade Afte r Selected) Figure 13-8. OSD Fade Function Example: Fade After 13-12 S3C880A/F880A ON-SCREEN DISPLAY COLUMNS 0-20 ROWS 0-11 A D G J M P B E H K N Q Line = 5 Line = 17 Fade Before (Fade Line = 5, Fade Line = Display) CHACON FADECON 06H (Fade Row = 6) 45H (Fade Line = 5; Fade Before Selected) Figure 13-9. OSD Fade Function Example: Fade Before 13-13 ON-SCREEN DISPLAY S3C880A/F880A DISPLAY POSITION CONTROL The on-screen display has 252 character display positions. There are 21 horizontal columns and 12 vertical rows. Positions can be numbered sequentially from 0-251 (decimal) or from 0-FB (hexadecimal), as shown in Figures 1311 and 13-12. To control display position, you can adjust the top and left margins and the inter-column and inter-row spacing between characters on the screen. COLUMNS 0-20 ROWS 0-11 ROWS 0-11 DECIMAL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 180 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 Figure 13-10. 252-Byte On-Screen Character Display Map (Decimal) COLUMNS 0-20 HEXADECIMAL 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 3F 54 69 7E 93 A8 BD D2 E7 2B 40 55 6A 7F 94 A9 BE D3 E8 2C 41 56 6B 80 95 AA BF D4 E9 2D 42 57 6C 81 96 AB C0 D5 EA 2E 43 58 6D 82 97 AC C1 D6 EB 2F 44 59 6E 83 98 AD C2 D7 EC 30 45 5A 6F 84 99 AE C3 D8 ED 31 46 5B 70 85 9A AF C4 D9 EE 32 47 5C 71 86 9B B0 C5 DA EF 33 48 5D 72 87 9C B1 C6 DB F0 34 49 5E 73 88 9D B2 C7 DC F1 35 4A 5F 74 89 9E B3 C8 DD F2 36 4B 60 75 8A 9F B4 C9 DE F3 37 4C 61 76 8B A0 B5 CA DF F4 38 4D 62 77 8C A1 B6 CB E0 F5 39 4E 63 78 8D A2 B7 CC E1 F6 3A 4F 64 79 8E A3 B8 CD E2 F7 3B 50 65 7A 8F A4 B9 CE E3 F8 3C 51 66 7B 90 A5 BA CF E4 F9 3D 52 67 7C 91 A6 BB D0 E5 FA 3E 53 68 7D 92 A7 BC D1 E6 FB Figure 13-11. 252-Byte On-Screen Character Display Map (Hexadecimal) 13-14 S3C880A/F880A ON-SCREEN DISPLAY ROW CONTROL REGISTER (ROWCON) The row control register, ROWCON, controls the top margin and inter-row spacing. Top margin is the distance (in Hsync pulses) to the top row of a character display from the top edge of its display frame. Inter-row spacing is the distance (in H-sync pulses) between two rows of displayed characters. The inter-row spacing value you select is applied equally to all rows in the display. OSD Row Control Register (ROWCON) F2H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Top margin display position control bits (4 x TMG value of 0-31 dots): 00000 = Top margin = 0H 00001 = Top margin = 4H 11111 = Top margin = 124H Inter-row spacing control bits (0H-7H in H-sync pulses): 000 = No inter-row spacing (0H) 001 = Inter-row spacing = 1H 111 = Inter-row spacing = 7H Figure 13-12. OSD Row Control Register (ROWCON) COLUMN CONTROL REGISTER (CLMCON) The column control register, CLMCON, controls the left margin and inter-column spacing. Left margin is the distance to the character display from the left edge of the display frame. Inter-column spacing is the distance (0-7 dots) between space separating the characters displayed in a row. The inter-column spacing value that you select is applied equally to all columns in the display. OSD Column Control Register (CLMCON) F3H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Left margin display position control value (16 + 4 x LMG value of 0-31 dots): 00000 = Left margin = 16 dots clock 00001 = Left margin = 16 + 4 x 1 dot clock 11111 = Left margin = 16 + 4 x 31 dot clock Inter-column spacing control value (0-7 dots): 000 = No inter-column spacing 001 = Inter-column spacing = 1 dot 111 = Inter-column spacing = 7 dots Figure 13-13. OSD Column Control Register (CLMCON) 13-15 ON-SCREEN DISPLAY S3C880A/F880A Top Margin Inter-Row Space Left Margin Inter-Column Space Figure 13-14. OSD Display Formatting and Spacing Conventions Calculating Row and Column Spacing Inter-row spacing and inter-column spacing are controlled by the ROWCON and CLMCON registers. You can select from zero to seven dots of spacing. For inter-row spacing, the desired spacing value (0-7) is written to bits 0-2 of the ROWCON register. For intercolumn spacing, the desired spacing value (0-7) is written to bits 0-2 of the CLMCON register. Calculating Margin Settings By writing a value to ROWCON.3-ROWCON.7, you can set the top margin at 4 x the top margin dot value (TMG). Because TMG is a 5-bit value, you can select any dot value in the range 0-31. By writing a value to CLMCON.3-CLMCON.7, you can set the left margin at 16 + 4 x the left margin dot value (LMG). Because LMG is a 5-bit value, you can select any dot value in the range 0-31. The zero position for the left margin is always 16 dots. -- Top margin = 4 x (top margin register value) H -- Left margin = 16 + 4 x (left margin register value) dot clock -- Inter-column space = (Register value) dot clock -- Inter-row space = (Register value) H 13-16 S3C880A/F880A ON-SCREEN DISPLAY CHARACTER COLOR CONTROL REGISTER (COLBUF) The color of the character matrix display is controlled by manipulating a 5-bit value in the OSD video RAM. You can modify the character color selection bits only by addressing the OSD color buffer register, COLBUF (FCH, set 1, bank 1). The color selection bits are COLBUF.2, COLBUF.1, COLBUF.0 and COLBUF.3 (H/T and BGRND). These four bits comprise the RGB value (bit 10, 11, 12) and H/T and BGRND enable bit (bit 13) of the character data stored in the video RAM. When programming the display RAM values for a character display, you must first load a 3-bit color value into the color buffer. This color setting is automatically appended to each 10-bit character code as it is written to the OSD RAM addresses. If only one COLBUF value is loaded, all characters in the screen display will, of course, be the same color. To change the display color of successive characters, modify the COLBUF value before you load the address data for a specific row and column into the video RAM. OSD Character Color Buffer (COLBUF) FCH, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used Video RAM bit 9 enable bit: 0 = Disable VRAM bit 9 1 = Enable VRAM bit 9 Video RAM bit 8 enable bit: 0 = Disable VRAM bit 8 1 = Enable VRAM bit 8 H/T and BGRND enable bit: 0 = Disable H/T and BGRND 1 = Enable H/T and BGRND (VRAM bit 13) Character color selection bits (.2 = red, .1 = green, .0 = blue) .2 0 0 0 0 1 1 1 1 .1 0 0 1 1 0 0 1 1 .0 0 1 0 1 0 1 0 1 Character color OSDCOL.0 = 0 OSDCOL.0 = 1 Black Color Mode 0 Blue Color Mode 1 Green Color Mode 2 Cyan Color Mode 3 Red Color Mode 4 Magenta Color Mode 5 Yellow Color Mode 6 White Color Mode 7 Figure 13-15. OSD Character Color Buffer Register (COLBUF) 13-17 ON-SCREEN DISPLAY S3C880A/F880A BACKGROUND COLOR CONTROL The background color control register, COLCON, lets you select background colors for both the display frame and characters: -- Frame background is the full-screen display field upon which the character display is imposed. -- Character background is a color field that surrounds the individual character. To enhance readability, the background is usually a color that contrasts or highlights the characters in a pleasing manner. Character Background Off Wide Screen Color TV Wide Screen Screen Color TV Color Wide Screen Color TV Frame Background Color Character Background Color No Character Background Color Figure 13-16. Background Color Display Conventions 13-18 S3C880A/F880A ON-SCREEN DISPLAY OSD Background Color Control Register (COLCON) F3H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Frame background color enable bit: 0 = Disable frame background color (No color is displayed) 1 = Enable frame background color Character color selection bits (See table) Character background color enable bit: 0 = Disable character background color (No color is displayed) 1 = Enable character background color Frame background color selection bit: .7 or .3 .6 or .2 .5 or .1 .4 or .0 0 1 1 1 1 1 1 1 1 x 0 0 0 0 1 1 1 1 x 0 0 1 1 0 0 1 1 x 0 1 0 1 0 1 0 1 Frame Character Background color OSDCOL.0 = 0 OSDCOL.0 = 1 No background display Black Color Mode 0 Blue Color Mode 1 Green Cyan Red Magenta Yellow White Color Mode 2 Color Mode 3 Color Mode 4 Color Mode 5 Color Mode 6 Color Mode 7 Figure 13-17. OSD Background Color Control Register (COLCON) 13-19 ON-SCREEN DISPLAY S3C880A/F880A V-SYNC BLANK CONTROL REGISTER (VSBCON) VSBCON sets the blank area, which stops the L-C oscillator during the defined time from the V-sync input time. Unit of V-sync blank time is 1 H-sync. It can be set up to a maximum of 31 H-syncs. If VSBCON.4 is set from"0" to "1001B", blank time is always 9 H-syncs regardless of the setting value. V-sync Blank Control Register (VSBCON) F7H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used V-sync blank time control bit: 00000 9 Horizontal sync 00001 9 Horizontal sync 00010 9 Horizontal sync 01001 9 Horizontal sync 01010 10 Horizontal sync 01011 11 Horizontal sync 11110 30 Horizontal sync 11111 31 Horizontal sync NOTE: Frame background is disabled during the V-sync blank time. Figure 13-18. V-sync Blank Control Register (VSBCON) 13-20 S3C880A/F880A ON-SCREEN DISPLAY V-SYNC BLANK AND TOP MARGIN TIMING DIAGRAM The following is a timing diagram simplified with external V-sync input and H-sync input signals. V-sync blank and top margin are controlled by VSBCON and ROWCON VSBCON .4-.0 = 01011B (V-sync blank time = 11 Horizontal sync). ROWCON.7-.3 = 00100B (top margin control value = 16, top margin = 5). V-sync blank V-sync input H-sync input H-line count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 1 2 3 4 Internal V-sync V-sync blank time on chip Top margin Row 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ROWCON.7-.3 (Top margin control value) V-sync interrupt Row 0 interrupt Figure 13-19. V-sync Blank and Top Margin Timing Diagram 13-21 ON-SCREEN DISPLAY S3C880A/F880A HALFTONE SIGNAL CONTROL REGISTER (HTCON) The halftone function lets you output halftone control signals to peripherals such as a chroma-IC. You can select halftone output for character back ground periods (as selected by bit 13 in the video RAM) or for frame periods (regardless of the bit 13 setting). The halftone signal control register, HTCON, has the following functions: -- Halftone option selection (character or frame) -- Halftone display enable/disable -- V-sync interrupt enable and pending control -- Polarity selection of RGB and halftone outputs Bits 4 and 5 are used for OSD Row interrupt function. OSD ROW Interrupt Control The S3C880A/F880A has a total of 12 OSD display rows. When enabled, an OSD ROW interrupt occurs in the first line of each row. Up to 12 OSD ROW interrupts can be generated, while this number can be reduced according to different settings in top margin (ROWCON.7-.3), inter row space (ROWCON.2-.0), vertical character size (CHACON.7-.6), and Vsync blank time (VSBCON). The ROW counter of DSPCON.7-.4 informs the order of an OSD ROW interrupt occurring within a frame. An OSD ROW interrupt is generated at the beginning of a ROW (for ROW0 through ROW11). OSD ROW interrupt allow different controls to each ROW. If the OSD control register is adjusted in the N-th row area, the new value is applied from (N+1)th row. That is, if the OSD control register is adjusted in the first OSD ROW interrupt (DSPCON.7-.4 = 0000B) service routine, the new value is applied from ROW1. A change in the 12 th OSD ROW interrupt service routine affects the rows from ROW0. NOTE: OSD output enable/disable (DSPCON.0) settings are immediately applied. Top margin (ROWCON.7-.3) and VSBCON are applied in accordance with Vsync input signals. Halftone Option Selection In character periods only (HTCON.2 = "0"), the character specified in COLBUF.3 may have the halftone function according to the condition of DSPCON.2-.1 (DSPCON.2-.1 = "10" or DSPCON.2-.1 = "11"). In all frame periods (HTCON.2 = "1"), the entire section can have the function, regardless of the COLBUF.3 condition. 13-22 S3C880A/F880A ON-SCREEN DISPLAY Halftone Signal Control Register (HTCON) F3H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Halftone signal output polarity selection bit: (1) 0 = Active high level 1 = Active low level RGB polarity selection bit: (2) 0 = Active high level 1 = Active low level OSD Row interrupt enable bit: 0 = Disable the OSD Row interrupt 1 = Enable the OSD Row interrupt OSD Row interrupt pending bit: 0 = No interrupt pending (when read) 0 = Clear pending bit (when write) 1 = Interrupt is pending (when read) 1 = No effect (when write) V-sync interrupt pending bit: 0 = No interrupt pending (when read) 0 = Clear pending bit (when write) 1 = Interrupt is pending (when read) 1 = No effect (when write) V-sync interrupt enable bit: 0 = Disable the V-sync interrupt 1 = Enable the V-sync interrupt Halftone option selection bit:(3) 0 = Character back ground periods only (when bit 3 of COLBUF is set to "1") 1 = All frame periods (disregard COLBUF "Bit 3") Halftone control signal enable bit: 0 = Disable halftone signal 1 = Enable halftone signal NOTES: 1. The HTCON.7 setting applies to halftone output only. The active high setting ("0") means that the normal halftone signal output is Low level. when you select the active low setting ("1"), the normal halftone signal output is High level. 2. The active high setting ("0") for HTCON.6 means that the normal RGB polarity is Low level. When you select the active low setting ("1"), the normal RGB polarity is High level. 3. In case HTCON.2 = 1, character halftone and background color (DSPCON.2-.1 = "11B") do not operate. Figure 13-20. Halftone Signal Control Register (HTCON) 13-23 ON-SCREEN DISPLAY S3C880A/F880A Background Color and Halftone Function Mode Character Color: Red Background Color: Blue SCAN Frame background color: Green COLCON.7 = "0", If OSDCOL.0 = "0", COLCON = 29H, HTCON.3-.2 ="10b" Frame background: Disable, Frame halftone: Disable, Character background: Enable with Blue color, Character background halftone: Enable R G B Blank OSDHT If OSDCOL.0 = "0", COLCON = A1H, HTCON.3-.2 ="11b" Frame background: Enable with Green coler, Frame halftone: Enable, Character background: Enable with Blue color, Character background halftone: Enable R G B Blank OSDHT Figure 13-21. Halftone or Character Backgound Signal Output 13-24 S3C880A/F880A ON-SCREEN DISPLAY OSD FIELD CONTROL REGISTER (OSDFLD) OSD field control register helps recognizing whether the current field is an EVEN field or an ODD one, in a TV signal frame. This control register must be defined for a current field recognition of V-sync and H-sync entering the S3C880A/F880A. In order to recognize an even field, OSDFLD.0-.3 defines the range starting from the point of V-sync edge, where H-sync must be present. If H-sync exits within the range, the field is recongnized as an EVEN field. OSDFLD.4 defines when H-sync must be detected. If it is set to "0", the existence of H-sync is detected within the range set by OSDFLD.0-.3 before V-sync is input. If it is set "1", it is detected after V-sync is input. OSDFLD.5 describes whether the current, field input by the field control which is set by OSDFLD.0-.3 and OSDFLD.4 is an EVEN field or an ODD one. OSD Field Control Register (OSDFLD) E5H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used Field data (read only): 0 = Even field 1 = Odd field H-sync detect position select: 0 = Detect H-sync before V-sync 1 = Detect H-sync after V-sync Even field range: 0000 = Not used 0001 = fCPU/16 x 1 0010 = fCPU/16 x 2 0011 = fCPU/16 x 3 0100 = fCPU/16 x 4 0101 = fCPU/16 x 5 0110 = fCPU/16 x 6 0111 = fCPU/16 x 7 1000 = fCPU/16 x 8 1001 = fCPU/16 x 9 1010 = fCPU/16 x 10 1011 = fCPU/16 x 11 1100 = fCPU/16 x 12 1101 = fCPU/16 x 13 1110 = fCPU/16 x 14 1111 = fCPU/16 x 15 Figure 13-22. OSD Field Control Register (OSDFLD) 13-25 ON-SCREEN DISPLAY S3C880A/F880A Field Detect by OSDFLD Control When control register set is OSDFLD.0-.3 = "1010B", OSDFLD.4 = 0 V-sync blank V-sync input H-sync input Even filed H-sync input fCPU/ 16 x 10 Odd filed Figure 13-23. Field Detect in Before V-sync V-sync blank V-sync input H-sync input Even filed V-sync input fCPU/ 16 x 10 Odd filed Figure 13-24. Field Detect in After V-sync 13-26 S3C880A/F880A ON-SCREEN DISPLAY OSD PALETTE COLOR CONTROL OSD Palette Color Mode Registers (OSDPLTR, OSDPLTG, OSDPLTB) OSD palette color mode register R, G, B controls the color of OSD R, G, B output. OSDPLTR1, OSDPLTR2, OSDPLTG1, OSDPLTG2, OSDPLTB1, and OSDPLTB2 are composed of 8 bits each, in which the combinations of bit0-bit1, bit2-bit3, bit4-bit5, bit6-bit7 of OSDPLTx1 (x = R, G, B) define color mode 0 to 3 and bit0-bit1, bit2-bit3, bit4-bit5, bit6-bit7 of OSDPLTx2 (x = R, G, B) define color mode 4 to 7, respectively. Each color mode can express upto 64 color by combing the six registers (OSDPLTR1, OSDPLTR2, OSDPLTG1, OSDPLTG2, OSDPLTB1, OSDPLTB2). As one color mode can select one color out of 64 choices, and there are 8 color modes, a total of 8 colors can be displayed at time. For example, when combining color mode 0, each of OSDPLTR1.0-1, and OSDPLTB1.0-1 can produce 4 kids of red level, which can be multiplied upto 64 combinations. Each 2 bits define a color mode make 4 color levels available. When the standard lighting is 100%, the value "00B" means disabled, "01B" means 33% and "10B" means 66% of the standard light level. OSD Palette Color Mode Register R1 (OSDPLTR1) E6H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB OSD mode 3 red level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 2 red level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 0 red level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 1 red level 00 = Disable 01 = 33% 10 = 66% 11 = 100% Figure 13-25. OSD Palette Color Mode Register R1 (OSDPLTR1) 13-27 ON-SCREEN DISPLAY S3C880A/F880A OSD Palette Color Mode Register R2 (OSDPLTR2) E7H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB OSD mode 7 red level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 6 red level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 4 red level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 5 red level 00 = Disable 01 = 33% 10 = 66% 11 = 100% Figure 13-26. OSD Palette Color Mode Register R2 (OSDPLTR2) 13-28 S3C880A/F880A ON-SCREEN DISPLAY OSD Palette Color Mode Register G1 (OSDPLTG1) E8H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB OSD mode 3 green level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 2 green level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 0 green level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 1 green level 00 = Disable 01 = 33% 10 = 66% 11 = 100% Figure 13-27. OSD Palette Color Mode Register G1 (OSDPLTG1) OSD Palette Color Mode Register G2 (OSDPLTG2) E9H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB OSD mode 7 green level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 6 green level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 4 green level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 5 green level 00 = Disable 01 = 33% 10 = 66% 11 = 100% Figure 13-28. OSD Palette Color Mode Register G2 (OSDPLTG2) 13-29 ON-SCREEN DISPLAY S3C880A/F880A OSD Palette Color Mode Register B1 (OSDPLTB1) EAH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB OSD mode 3 blue level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 2 blue level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 0 blue level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 1 bluelevel 00 = Disable 01 = 33% 10 = 66% 11 = 100% Figure 13-29. OSD Palette Color Mode Register B1 (OSDPLTB1) OSD Palette Color Mode Register B2 (OSDPLTB2) EBH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB OSD mode 7 blue level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 6 blue level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 4 blue level 00 = Disable 01 = 33% 10 = 66% 11 = 100% OSD mode 5 bluelevel 00 = Disable 01 = 33% 10 = 66% 11 = 100% Figure 13-30. OSD Palette Color Mode Register B2 (OSDPLTB2) 13-30 S3C880A/F880A ON-SCREEN DISPLAY OSD SPACE COLOR CONTROL REGISTER (OSDCOL) RGB output selection S3C880A/F880A has two RGB output mode: digital mode and analog mode. In Digital mode, OSDCOL.0 must be set to 0. RGB output has two levels, VSS and VDD. Eight colors can be produced: black, blue, green, cyan, red, magenta, yellow and white. OSD palette color control registers, OSDPLTR1, OSDPLTR2, OSDPLTG1, OSDPLTG2, OSDPLTB1, and OSDPLTB2, are not used in this mode. In analog mode, OSDCOL.0 must be set to 1. R.G.B output color bright can be selected among four levels respectively. 64 colors can be selected by setting OSD palette color control registers, OSDPLTR1, OSDPLTR2, OSDPLTG1, OSDPLTG2, OSDPLTB1, and OSDPLTB2. In one display row you can select 8 colors, color mode 0-7, by setting COLBUF.2-.0. The color selected by color mode 0-7 can be changed in every display row. Inter-row space halftone Inter-row spacing is the distance (in H-sync pulses) between two rows of displayed characters and can be changed by setting ROWCON.2-.0. Also halftone character can be changed for this inter-row spacing. For OSDCOL.1=0, halftone function of inter-row space region is the same as that of the character background region. That is, if the halftone function of character background region is enabled by setting HTCON.3 to "1", the halftone function of inter-row space region is enabled. When HTCON.3 is set to "1", halftone function of character background is enabled regardless of the value of HTCON.2. For OSDCOL=1 (depend on frame background halftone), inter-row space halftone function is enabled when the value of HTCON.3 and HTCON.2 are set to "1". Inter-row space color Inter-row space color depends on the character background color and frame background color by COLCON. When OSDCOL.2 is "0", inter-row space color depends on the current character background color; when OSDCOL.2 is "1", inter-row space color depends on the current frame background color. Fringe dot size selection 1 dot (when OSDCOL.3 is "0") is a fringe size, which is set by OSDFRG1 and OSDFRG2. For 1/2 dot fringe size (when OSDCOL.3 is "1"), fringe function is set by 1/2 dot unit. In the interlaced scan, even field line and odd field line are added to form 1 dot of length. If character size of length is x1 or x3 in the 1/2 dot fringe size, blinking can occur. So, 1 dot fringe size method is recommended. Inter character smoothing control If inter character smoothing is enabled (when OSDCOL.4 is "1"), adjacent character is considered as one character and smoothing function is enabled. 13-31 ON-SCREEN DISPLAY S3C880A/F880A OSD Space Color Control Register (OSDCOL) E4H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used Inter character smoothing control bit (note) : 0 = Disable inter character smoothing 1 = Enable inter character smoothing RGB output selection bit: 0 = Digital RGB output (Disable palette color mode) 1 = Analog RGB output (Enable palette color mode) Inter-row space halftone 0 = Depend on character background halftone 1 = Depend on frame background halftone Fringe dot size selection bit: Inter-row space color 0 = 1 dot 0 = Depend on character background color 1 = 1/2 dot 1 = Depend on frame background color Figure 13-31. OSD Space Color Control Register (OSDCOL) 13-32 S3C880A/F880A ON-SCREEN DISPLAY OSD BORDER/FRINGE FUNCTION Fringing Function The fringing function is used to display a character with a fringe (fringe means shadowed character at bottom and right direction) width is 1 or 1/2 dot in a different color from that of the character. For all character size, fringe width is 1 or 1/2 dot by set of OSDCOL.3. When a character is displayed with the maximum of 18 vertical dots and 16 horizontal dots, the fringe exceeds right and bottom of the character display area. The exceeded fringe can be displayed; however , display characters have higher priority to fringe. In this case, If you want to display both fringe and character, you should set inter-row space and inter-column space. When 1dot fringe function is selected, you should set minimum two dots of inter-row space or inter-column space. When 1/2 dot fringe function is selected, you should set minimum one dot of inter-row space or inter-column space. Fringing is enabled for each line by setting each bit of OSDFRG1 and OSDFRG2 to "1" when OSDFRG2.7="1". Three bits of OSDFRG2.6-.4 are control Border color. A color for fringe is specified common to selected row and a color for fringe to each row are controlled differently. NOTE: When Vertical size x1 and x3 in 1/2 fringe enabled, the flickering may be generated. Because vertical 1 dot means even and odd field, that is 1/2 dot is even or odd field area. So interlace scan TV system, you can see the flickering. Border Function The Border function is used to display a character with a Border (Border means shadowed at all character boundary) width is 1/2 dot in a different color from that of the character. For all character size, Border width is 1/2 dot. When a character is displayed with the maximum of 18 vertical dots and 16 horizontal dots, the fringe exceeds right and bottom of the character display area. The exceeded Border can be displayed; however , display characters have higher priority to fringe. In this case, If you want to display both Border and character, you should set inter-row space and inter-column space over minimum one dot. Border is enabled for each line by setting each bit of OSDFRG1 and OSDFRG2 to "1" when OSDFRG2.7="0". Three bits of OSDFRG2.6-.4 are control Border color. A color for Border is specified common to selected row and a color for fringe to each row are controlled differently. NOTE: When Vertical size x1 and x3, the flickering may be generated. Because vertical 1 dot means even and odd field, that is 1/2 dot is even or odd field area. So interlace scan TV system, you can see the flickering. 13-33 ON-SCREEN DISPLAY S3C880A/F880A OSD Fringe/Border Control Register 1 (OSDFRG1) E0H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Fringe/Border function enable bit: 0 = Disable fringe/border function at row n (n = 0-7) 1 = Enable fringe/border function at row n (n = 0-7) Figure 13-32. OSD Fringe/Border Control Register 1 (OSDFRG1) OSD Fringe/Border Control Register 2 (OSDFRG2) E1H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Fringe or Border selection bit: 0 = Border function select 1 = Fringe function select Fringe/Border function enable bit: 0 = Disable fringe/border function at row n (n = 8-11) 1 = Enable fringe/border function at row n (n = 8-11) Fringe/Border color selection bits: (.6 = red, .5 = green, .4 = blue) .6 0 0 0 0 1 1 1 1 .5 0 0 1 1 0 0 1 1 .4 0 1 0 1 0 1 0 1 Fringe/Border Color OSDCOL.0 = 0 OSDCOL.0 = 1 Black Color Mode 0 Blue Color Mode 1 Green Color Mode 2 Cyan Color Mode 3 Red Color Mode 4 Magenta Color Mode 5 Yellow Color Mode 6 White Color Mode 7 Figure 13-33. OSD Fringe/Border Control Register 2 (OSDFRG2) 13-34 S3C880A/F880A ON-SCREEN DISPLAY OSD SMOOTH FUCNTION Smoothing function The smoothing function is used to make characters look smooth. Enabling smoothing displays 1/4 dot between two dots connecting corner to corner within a character. Smoothing is enabled by setting each bit of OSDSMH1 and OSDSMH2 to "1". A smooth is specified common to selected row. OSD Smooth Control Register 1(OSDSMH1) E2H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Row 7 smooth function enable bit: 0 = Disable smooth function at Row 7 1 = Enable smooth function at Row 7 Row 6 smooth function enable bit: 0 = Disable smooth function at Row 6 1 = Enable smooth function at Row 6 Row 5 smooth function enable bit: 0 = Disable smooth function at Row 5 1 = Enable smooth function at Row 5 Row 4 smooth function enable bit: 0 = Disable smooth function at Row 4 1 = Enable smooth function at Row 4 Row 0 smooth function enable bit: 0 = Disable smooth function at Row 0 1 = Enable smooth function at Row 0 Row 1 smooth function enable bit: 0 = Disable smooth function at Row 1 1 = Enable smooth function at Row 1 Row 2 smooth function enable bit: 0 = Disable smooth function at Row 2 1 = Enable smooth function at Row 2 Row 3 smooth function enable bit: 0 = Disable smooth function at Row 3 1 = Enable smooth function at Row 3 Figure 13-34. OSD Smooth Control Register 1 (OSDSMH1) 13-35 ON-SCREEN DISPLAY S3C880A/F880A OSD Smooth Control Register 2 (OSDSMH2) E3H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used Row 8 smooth function enable bit: 0 = Disable smooth function at Row 8 1 = Enable smooth function at Row 8 Row 9 smooth function enable bit: 0 = Disable smooth function at Row 9 1 = Enable smooth function at Row 9 Row 10 smooth function enable bit: 0 = Disable smooth function at Row 10 1 = Enable smooth function at Row 10 Row 11 smooth function enable bit: 0 = Disable smooth function at Row 11 1 = Enable smooth function at Row 11 Figure 13-35. OSD Smooth Control Register 2 (OSDSMH2) (a) Smoothing (b) Bordering (c) Priority of Smoothing and Bordering (d) Fringing (1 dot) Figure 13-36. Smoothing/Fringing/Priority of Smoothing and Fringing 13-36 S3C880A/F880A ON-SCREEN DISPLAY F PROGRAMMING TIP -- Row Interrupt Function This example shows the effect of the control register setting excluding the HTCON.5,4,1,0 and DSPCON 3,0 occurs in the next row. The sample program should meet the following specifications: 1. 2. The character size of the row 2 must be double-sized (x 2). The character size of the other rows must be normal (x 1). V-sync interrupt OSD Row interrupt SB1 SB1 DSPCON #01H PUSH R0 CHACON #00H R0 DSPCON HTCON #32H AND R0, #0F0H IRET R0 = 10H Yes CHACON #50H No CHACON #00H POP R0 HTCON #23H IRET Figure 13-37. Decision Flowchart for Row Interrupt Function Programming Tip 13-37 ON-SCREEN DISPLAY S3C880A/F880A F PROGRAMMING TIP -- Row Interrupt Function (Continued) Vsync_int: SB1 LD DSPCON,#01H ;This is Vsync interrupt service routine. Interrupt_end: LD IRET Row_int: SB1 PUSH LD AND CP JR LD JR No_char_change: LD Row_interrupt_end: POP LD IRET R0 R0,DSPCON R0,#0F0H R0,#10H NE, No_Char_Change CHACON,#50H t, Row_interrupt_end ; ; ; ; ; ; Select bank 1 Stack R0 R0 DSPCON data 11110000b, bit0-bit3 clear Row 1 interrupt? Double size character at row 2 HTCON, #32H ; Pending bit clear ; Select bank 1 ; OSD on, H/V sync rising edge CHACON, #00H ; X1 size character except row 2 R0 HTCON, #23H ; Pending bit clear 13-38 S3C880A/F880A ON-SCREEN DISPLAY F PROGRAMMING TIP -- Writing Character Code and Color Data to the OSD Video RAM This example shows how to write character code and color data to the OSD video RAM. The sample program performs the following operations: 1. 2. Write red character 'A' (code 0A, for example) to the video RAM from address 00H to 77H. Write green character 'B' (code 0B, for example) to the video RAM from address 78H to 0FBH. * * * OSDLP1 OSDLP2 SB1 LD LD LD SRP0 LD CLR LD INC CP JP LD LD INC CP JP SB0 * * * DSPCON,#0F9H OSDCOL,#0 PP,#11H #0C0H COLBUF,#04H R0 @R0,#0AH R0 R0,#77H ULE,OSDLP1 COLBUF,#02H @R0,#0BH R0 R0,#0FBH ULE,OSDLP2 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Select bank 1 OSD module on; negative sync trigger is selected Digital RGB selection Select OSD video RAM page (page 1) Select common working register area Load color buffer (red color) Load starting address (00H) to R0 Write red character A to video RAM address 00H-77H " " " Load green color code (02H) to the color buffer Write green character B to RAM address 78H-0FBH " " " Select bank 0 F PROGRAMMING TIP -- OSD Fade Function; Line and Row Counters This example is a continuation of the previous OSD example in which character code and color data were written to the video RAM. Assuming a timer A interrupt interval of 2 milliseconds, the sample program should meet the following specifications: 1. 2. 3. If bit fade (R4.0) is set, then enable the fade function. Interval time between two lines = 20 ms. (The flag 'INTVAL' is set at 20-ms intervals in the timer A service routine.) Fade direction is 'fade after'. 13-39 ON-SCREEN DISPLAY S3C880A/F880A FADECON No ("0") Fade = "1"? Yes ("1") F_STRT "1" F_STRT = "1"? No ("0") Yes (Initial) Exit No ("0") Exit INTVAL = "1"? Yes ("1") ROWCNT LINECNT F_STRT #00H #00H "1" LINECNT LINECNT + #1 INTVAL "1" Y (> #19) = N (< #19) LINECNT = #19? LINECNT #00H ROWCNT ROWCNT + 1 N (< #12) ROWCNT = #11? Enable Fade Fade 0 Disable Fade Function OSD ON Exit Figure 13-38. Decision Flowchart for Fade Function Programming Tip 13-40 S3C880A/F880A ON-SCREEN DISPLAY F PROGRAMMING TIP -- OSD Fade Function; Line and Row Counters (Continued) EQU EQU EQU EQU EQU EQU * * * ROWCNT LINECNT FADE F_STRT INT_CNT INTVAL 6 7 0 1 5 2 SB1 LD SRP0 BTJRF BTJRT BTJRF INC BITR CP JP CLR INC CP JP LD LD BITR LD FAD3 LD JR PP,#11H #0C0H EXIT1,R4.FADE FAD1,R4.F_STRT EXIT,R4.INTVAL RLINECNT R4.INTVAL RLINECNT,#13H ULT,FAD2 RLINECNT RROWCNT RROWCNT,#0DH ULT,FAD2 R1,#0F1H R2,@R1 R2.6 @R1,R2 DSPCON,#0F9H T,EXIT ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Select bank 1 Select OSD video RAM page (page 1) RP0 0C0H (common working register area) If flag FADE = "0", then jump to EXIT1 If F_STRT = "1", then jump to FAD1 If INTVAL = "1", then jump to EXT Line counter line counter + 1 INTVAL "0" Line counter 19? If line counter < 19, then jump to FAD2 Line counter "0" Row counter row counter + 1 Row counter < 11? If row 12, then jump to FAD2 If row > 12, then finish the fade function ; Fade disable ; OSD module on (Continued on next page) 13-41 ON-SCREEN DISPLAY S3C880A/F880A F PROGRAMMING TIP -- OSD Fade Function; Line and Row Counters (Continued) FAD1 CLR CLR BITS LD AND OR LD INC LD OR LD JR BITS SB0 * * * RROWCNT RLINECNT R4.F_STRT R2,CHACON R2,#0F0H R2,RROWCNT CHACON,R2 R1 R2,RLINECNT R2,#60H FADECON,R2 T,FAD3 R4.F_STRT ; Row counter (R6) 0H ; Line counter (Rn) 0H R2 CHACON Clear the fade row address Load new fade row address to R2 CHACON R2 R1 0F1H (fade line address) R2 new fade line address Enable fade function, select fade after FAD2 ; ; ; ; ; ; ; EXIT1 EXIT ; Select bank 0 TAINT PUSH PUSH LD SRP0 INC CP JP CLR BITS NOP * * * PP RP0 PP,#11 #0C0H RINT_CNT RINT_CNT,#0AH ULE,TA1 RINT_CNT R4.INTVAL ; ; ; ; ; ; ; Select video RAM page (page 1) RP0 0C0H Interval counter interval counter + 1 Interval counter 10? (Has 20 ms elapsed?) If yes, then jump to TA1 20 ms has elapsed, so clear interval counter INTVAL "1" TA1 POP POP IRET RP0 PP 13-42 S3C880A/F880A ON-SCREEN DISPLAY F PROGRAMMING TIP -- Manipulating OSD Character Colors; Halftone Function This example is a continuation of the previous OSD examples. Following the second sample program, red character A is in the video RAM address 00H-77H and green character B has been written to addresses 78H-0EFH. The program performs the following additional actions: 1. 2. 3. Change the color of character 'A' to white. Change the color of character 'B' to its complementary color. Enable the halftone function for character 'B'. * * * SB1 LD SRP0 LD CLR LD INC CP JP LD COM AND LD LD * * * PP,#11H #0C0H COLBUF,#0FH R0 @R0,#0AH R0 R0,#77H ULE,OSDLP1 R2,COLBUF R2 R2,#0FH COLBUF,R2 DSPCON,#0F9H OSDLP1 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Select bank 1 Select video RAM page (page 1) RP0 0C0H (common working register area) Color buffer white color code (07H), character background enable R0 (video RAM address) 00H Video RAM (00H-77H) white 'A' " " " R2 color buffer (color of character in address 78H) R2 (not R2) Mask out bit 7 through bit 3 of R2 Color buffer complementary color of the character in address 78H OSD module on; negative sync trigger selected (Continued on next page) 13-43 ON-SCREEN DISPLAY S3C880A/F880A F PROGRAMMING TIP -- Manipulating Character Colors; Halftone Function (Continued) CALL * * * halftone halftone1 ; Halftone signal control halftone1 PUSH PUSH PUSH SB1 LD SRP0 CLR PP RP0 FLAGS PP,#11H #20H R0 ; ; ; ; ; ; ; Stack PP Stack RP0 Save flags to stack Select bank 1 Page 1 selected RP0 20H (working register area) R0 00H loop_halftone LD LD LD INC CP JP tm JR LD LD HTCON,#02H DSPCON,#09H R1,@R0 R0 R0,#0FBH UGT,end_halftone COLBUF,#08H Z,loop_halftone HTCON,#0AH DSPCON,#0DH ; ; ; ; Disable halftone control register Enable V-sync interrupt Enable OSD; select negative sync trigger Video RAM zero address ; Video RAM end? ; Check COLBUF.3 (character background enable?) ; ; ; ; ; Enable halftone Enable V-sync interrupt Halftone output mode Select negative sync trigger No line is double size JP end_halftone POP POP POP RET * * * t,loop_halftone FLAGS RP0 PP ; ; ; ; Restore flag values from stack Restore register pointer 0 value Restore page pointer Return 13-44 S3C880A/F880A ON-SCREEN DISPLAY F 1. 2. 3. 4. PROGRAMMING TIP -- OSD Character Size, Background Color, and Display Position This example is a continuation of the previous OSD examples. It performs the following additional actions: Change the character size to horizontal x3 and vertical x2. Enable character background color to the complementary color of the character code in address 0EFH of the video RAM. Enable the frame background; select the color cyan. Set top margin to 16H, inter-row spacing to 1H, left margin to 24 dots, and inter-column spacing to three (3) dots. * * * SB1 LD SRP0 LD LD LD LD LD LD COM AND OR LD LD SB0 * * * PP,#11H #0C0H COLCON,#0 CHACON,#60H FADECON,#00H ROWCON,#21H CLMCON,#1BH R3,COLBUF R3 R3,#07H R3,#0B8H COLBUF,R3 DSPCON,#09H ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Select bank 1 Select video RAM page (page 1) Select common working register area Digital RGB selection Horizontal x3, vertical x2 for character size Disable the fade function Top margin 16H, inter-row space 1H Left margin 24 dots, inter-column space 3 dots R3 color of the character in address 0EFH R3 not R3 Mask out bit 7 through bit 3 of R3 R3 cyan frame background color Enable character and frame background color Falling edge sync trigger, OSD on Select bank 0 F PROGRAMMING TIP -- Helpful Hints About COLBUF and OSD Character Code 0 When working with the OSD module, please note the somewhat unusual characteristics of the color buffer register (COLBUF) and the OSD character code 0: -- The color buffer register, COLBUF (F7C, set 1, bank 1) provides a somewhat unusual method for manipulating character color data. -- OSD character code 0 produces a no-display and no-background condition, regardless of the font coding used. 13-45 ON-SCREEN DISPLAY S3C880A/F880A NOTES 13-46 S3C880A/F880A A/D CONVERTER 14 OVERVIEW ANALOG-TO-DIGITAL CONVERTER The 8-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 8-bit digital values. The analog input level must lie between the VDD and VSS values. The A/D converter has the following components: -- Analog comparator with successive approximation logic -- D/A converter logic (resistor string type) -- ADC control register (ADCON) -- Four multiplexed analog data input pins (ADC0-ADC3) -- 8-bit A/D conversion data output register (ADDATA) To initiate an analog-to-digital conversion procedure, you write the channel selection data in the A/D converter control register ADCON to select one of the four analog input pins (ADCn, n = 0-3) and set the conversion start or enable bit, ADCON.0. The read-write ADCON register is located at address FAH. During a normal conversion, A/D C logic initially sets the successive approximation register to 80H (the approximate half-way point of an 8-bit register). This register is then updated automatically during each conversion step. The successive approximation block performs 8-bit conversions for one input channel at a time. You can dynamically select different channels by manipulating the channel selection bit value (ADCON.5-4) in the ADCON register. To start the A/D conversion, you should set a the enable bit, ADCON.0. When a conversion is completed, ADCON.3, the end-of-conversion (EOC) bit is automatically set to 1 and the result is dumped into the ADDATA register where it can be read. The A/D converter ten enters an idle state. Remember to read the contents of ADDATA before another conversion starts. Otherwise, the previous result will be overwritten by the next conversion result. NOTE Because the ADC does not use sample-and-hold circuitry, it is important that any fluctuations in the analog level at the ADC0-ADC3 input pins during a conversion procedure be kept to an absolute minimum. Any change in the input level, perhaps due to circuit noise, will invalidate the result. 14-1 A/D CONVERTER S3C880A/F880A USING A/D PINS FOR STANDARD DIGITAL INPUT The ADC module's input pins are alternatively used as digital input in port 0 and port 3. The ADC0-ADC1 share pin names are P3.0-P3.1 and ADC2-ADC3 share pin names are P0.6-P0.7, respectively. A/D CONVERTER CONTROL REGISTER (ADCON) The A/D converter control register, ADCON, is located at address FAH. Only bits 5-0 are used in the S3C880A/F880A implementation. ADCON has three functions: -- Bits 5-4 select an analog input pin (ADC0-ADC3). -- Bit 3 indicates the status of the A/D conversion. -- Bit 2-1 select a conversion speed. -- Bit 0 starts the A/D conversion. Only one analog input channel can be selected at a time. You can dynamically select any one of the four analog input pins (ADC0-ADC3) by manipulating the 2-bit value for ADCON.5-ADCON.4. A/D Converter Control Register (ADCON) FAH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used Conversion start bit: 0 = No effect 1 = A/D conversion start Clock source selection bit: 00 = f OSC/16 01 = f OSC/8 10 = f OSC/4 11 = f OSC/2 Analog input pin selection bits: 00 = ADC0 (P3.0) 01 = ADC1 (P3.1) 10 = ADC2 (P0.6) 11 = ADC3 (P0.7) End-of-conversion status bit: (Read only) 0 = A/D conversion is in progress 1 = A/D conversion complete Figure 14-1. A/D Converter Control Register (ADCON) 14-2 S3C880A/F880A A/D CONVERTER INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range AVSS to AVREF (usually, AVREF = VDD). Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. The reference voltage level for the first bit conversion is always 1/2 AVREF. A/D Converter Control Register ADCON (FAH) ADCON .5-4 ADCON .0 (ADEN) Control Circuit ADC0/P3.0 ADC1/P3.1 ADC2/P0.6 ADC3/P0.7 Successive Approximation Circuit ADCON .2-1 Clock Selector ADCON .3 (EOC Flag) _ Analog Comparator Conversion Result D/A Converter AVREF AVSS ADDATA (FBH) To Data Bus Figure 14-2. A/D Converter Circuit Diagram ADDATA (FBH) .7 .6 .5 .4 .3 .2 .1 .0 Figure 14-3. A/D Converter Data Register (ADDATA) 14-3 A/D CONVERTER S3C880A/F880A Conversion Start tCON = 50 CPU Clock EOC ADDATA Previous Value Valid Data Value Remains Undetermined Figure 14-4. S3C880A/F880A A/D Converter Timing Diagram CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 18 clocks to step-up A/D conversion. Therefore, total of 50 clocks are required to complete an 8-bit conversion: With an 10 MHz CPU clock frequency, one clock cycle is 100 ns. If each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 8-bits + step-up time (18 clock) = 50 clocks 50 clock x 100 ns = 5 s at 10 MHz, 1 clock time = CPU clock INTERNAL A/D CONVERSION PROCEDURE 1. 2. 3. 4. 5. 6. Analog input must remain between the voltage range of AVSS and AVREF. Configure the analog input pins to input mode by making the appropriate settings in P3CONL and P0CONH registers. Before the conversion operation starts, you must first select one of the four input pins (ADC0-ADC3) by writing the appropriate value to the ADCON register. When conversion has been completed, (50 CPU clocks have elapsed), the EOC flag is set to "1", so that a check can be made to verify that the conversion was successful. The converted digital value is loaded to the output register, ADDATA, than the ADC module enters an idle state. The digital conversion result can now be read from the ADDATA register. 14-4 S3C880A/F880A A/D CONVERTER VDD Reference Voltage Input R AVREF VDD 104 Analog Input Pin ADC0-ADC3 101 S3F880A AVSS VSS NOTE: The symbol 'R' signifies an offset resistor with a value of from 50 to 10 Ohm. 0 Figure 14-5. Recommended A/D Converter Circuit for Highest Absolute Accuracy F PROGRAMMING TIP - Configuring A/D Converter * * * LD LD * * * P3CONL,#00000101B P0CONH,#01010000B ; P3.1-0 A/D Input MODE ; P0.7-6 A/D Input MODE AD0_CHK: LD TM JR LD * * ADCON,#00000001B ADCON,#00001000B Z,AD0_CHK AD0BUF,ADDATA ; channel ADC0: P3.0/conversion start ; A/D conversion end ? EOC check ; no ; Conversion data AD1_CHK: LD TM JR LD * * ADCON,#00010001B ADCON,#00001000B Z,AD1_CHK AD1BUF,ADDATA ; channel ADC1: P3.1/conversion start ; A/D conversion end ? EOC check ; no ; Conversion data 14-5 A/D CONVERTER S3C880A/F880A NOTES 14-6 S3C880A/F880A ELECTRICAL DATA 15 OVERVIEW -- I/O capacitance ELECTRICAL DATA In this section, S3C880A/F880A electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- D.C. electrical characteristics -- A.C. electrical characteristics -- Input timing measurement points for tNF1 and tNF2 -- Data retention supply voltage in Stop mode -- Stop mode release timing when initiated by nRESET -- Main oscillator and L-C oscillator frequency -- Clock timing measurement points for XIN -- Main oscillator clock stabilization time (t ST) -- A/D converter electrical characteristics -- Characteristic curves 15-1 ELECTRICAL DATA S3C880A/F880A Table 15-1. Absolute Maximum Ratings (TA = 25C) Parameter Supply Voltage Input Voltage Symbol VDD VI1 VI2 Output Voltage Output Current High VO IOH Conditions - P1.0-P1.5 (open-drain) All port pins except VI1 All output pins One I/O pin active All I/O pins active Output Current Low IOL One I/O pin active Total pin current for port 1 Total pin current for ports 0, 2, and 3 Operating Temperature Storage Temperature TA TSTG - - Rating - 0.3 to + 6.0 - 0.3 to + 7 - 0.3 to VDD + 0.3 Unit V V - 0.3 to VDD + 0.3 - 18 - 60 + 30 + 100 + 100 - 20 to + 85 - 65 to + 150 V mA mA C C Table 15-2. D.C. Electrical Characteristics (TA = - 20C to + 85C, VDD = 4.5 V to 5.5 V) Parameter Input High Voltage Input Low Voltage Symbol VIH1 VIH2 VIL1 VIL2 Output High Voltage Output Low Voltage VOH Conditions All input pins except VIH2 XIN, XOUT Min 0.8 VDD 2.7 V - Typ - Max VDD Unit V All input pins except VIL2 XIN, XOUT IOH = - 500 A P0.0-P0.5, P1.6-P1.7, P2 R, G, B (digital level), Vblank - 0.2 VDD 1.0 V V VDD - 0.8 - - V VOL1 VOL2 VOL3 VOL4 IOL = 4 mA P0.0-P0.5, P1.6-P1.7 IOL = 10 mA P1.4-P1.5 IOL = 2 mA P1.0-P1.3, P3.0-P3.1, P0.6-P0.7 IOL = 1 mA R, G, B (digital level), Vblank, P2 - - - - - - - - 0.5 0.8 0.5 0.4 V V 15-2 S3C880A/F880A ELECTRICAL DATA Table 15-2. D.C. Electrical Characteristics (Continued) (TA = - 20C to + 85C, VDD = 4.5 V to 5.5 V) Parameter Input High Leakage Current Symbol ILIH1 Conditions VIN = VDD All input pins except ILIH2 and ILIH3 VIN = VDD, OSCIN, OSCOUT VIN = VDD, XIN, XOUT VIN = 0 V All input pins except ILIL2, ILIL3, and nRESET ILIL2 ILIL3 Output High Leakage Current ILOH1 ILOH2 Output Low Leakage Current Supply Current (note) Min - Typ - Max 1 Unit A ILIH2 ILIH3 Input Low Leakage Current ILIL1 10 2.5 - 10 - 20 -1 A VIN = 0 V, OSCIN, OSCOUT VIN = 0 V, XIN, XOUT VOUT = VDD All output pins except ILOH2 VOUT = 6 V P1.0-P1.5 VOUT = 0 V All output pins Normal mode; VDD = 4.5 V to 5.5 V 8-MHz CPU clock Idle mode; VDD = 4.5 V to 5.5 V 8-MHz CPU clock Stop mode; VDD = 4.5 V to 5.5 V - - - 7 - 2.5 - - 10 - - 10 - 20 1 A 10 -1 20 A mA ILOL IDD1 IDD2 4 10 IDD3 NOTE: loads. 1 10 A Supply current does not include the current drawn through internal pull-up resistors or external output current 15-3 ELECTRICAL DATA S3C880A/F880A Table 15-3. Input/Output Capacitance (TA = - 20C to + 85C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are connected to VSS Min - Typ - Max 10 Unit pF Table 15-4. A.C. Electrical Characteristics (TA = - 20C to + 85C, VDD = 4.5 V to 5.5 V) Parameter V-sync Pulse Width H-sync Pulse Width Noise Filter Symbol tVW tHW tNF1 tNF2 tNF3 tNF4 NOTE: fCAPA = fOSC/128. Conditions - - P1.0-P1.3, H-sync, V-sync nRESET Glitch filter (oscillator block) CAPA Min 4 3 - - - - Typ - - 350 1000 25 5 Max - - - Unit s s ns - tCAPA Table 15-5. Analog R,G,B Output (TA = - 20C to + 85C, VDD = 4.75 V to 5.25 V) Output Voltage (50 k load) VDD = 4.75 V Data = 11 Data = 10 Data = 01 Data = 00 4.00 V 0.30 V 3.10 V 0.25 V 1.90 V 0.20 V 0.00 V - 0.65 V VDD = 5.00 V 4.20 V 0.30 V 3.35 V 0.25 V 2.00 V 0.20 V 0.00 V - 0.75 V VDD = 5.25 V 4.40 V 0.30 V 3.40 V 0.25 V 2.10 V 0.20 V 0.00 V - 0.75 V Remark 15-4 S3C880A/F880A ELECTRICAL DATA 1tCPU tNF1L tNF2 0.8 VDD 0.2 VDD tNF2H Figure 15-1. Input Timing Measurement Points for tNF1 and tNF2 Table 15-6. Data Retention Supply Voltage in Stop Mode (TA = - 20 C to + 85 C) Parameter Data Retention Supply Voltage Data Retention Supply Current Symbol VDDDR IDDDR Stop mode Stop mode, VDDDR = 2.0 V Conditions Min 2 - Typ - - Max 6 5 Unit V A NOTES: 1. Supply current does not include the current drawn through internal pull-up resistors or external output current loads. 2. During the oscillator stabilization wait time (tWAIT), all the CPU operations must be stopped. RESET Occurs Stop Mode Data Retention Mode VDD Oscillation Stabilization Time Normal Operating Mode Execution of STOP Instrction nRESET 0.2 VDD NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC tWAIT Figure 15-2. Stop Mode Release Timing When Initiated by a nRESET ~ ~ ~ ~ VDDDR 15-5 ELECTRICAL DATA S3C880A/F880A Table 15-7. Main Oscillator and L-C Oscillator Frequency (TA = - 20C + 85C, VDD = 4.5 V to 5.5 V) Oscillator Crystal Clock Circuit XIN XOUT Conditions OSD block active Min 5 Typ 6 Max 8 Unit MHz C1 C2 OSD block inactive Ceramic XIN XOUT 0.5 5 6 6 8 8 MHz OSD block active C1 C2 OSD block inactive External Clock XIN XOUT 0.5 5 6 6 8 8 MHz OSD block active OSD block inactive L-C Oscillator OSCIN OSCOUT 0.5 5 6 6.5 8 8 MHz Recommend value; C1 = C2 = 20 pF C1 C2 CPU Clock Frequency - 0.032 6.0 8 MHz 1/fOSC tXL XIN tXH 2.7 V 1.0 V Figure 15-3. Clock Timing Measurement Points for XIN 15-6 S3C880A/F880A ELECTRICAL DATA Table 15-8. Main Oscillator Clock Stabilization Time (TA = - 20C + 85C, VDD = 4.5 V to 5.5 V) Oscillator Crystal Ceramic Symbol - Test Condition VDD = 4.5 V to 6.0 V (Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range.) External Clock XIN input High and Low level width (t XH, tXL) Release Signal Setup Time Oscillation Stabilization Wait Time (1) tSREL tWAIT Normal operation CPU clock = 8 MHz; Stop mode released by nRESET CPU clock = 8 MHz; Stop mode released by an interrupt - - 1000 8.3 (2) Min - Typ - Max 20 10 Unit ms 65 - 100 ns - - ns ms NOTES: 1. Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a power-on occurs, or when Stop mode is released. 2. The oscillation stabilization interval is determined by the basic timer (BT) input clock setting. 15-7 ELECTRICAL DATA S3C880A/F880A Table 15-9. A/D Converter Electrical Characteristics (TA = - 20C to + 85C, VDD = 4.5 V to 5.5 V, VSS = 0 V) Parameter Absolute Accuracy Symbol Test Conditions VDD = 5.12 V CPU CLOCK = 8 MHz AVREF = 5.12 V AVSS = 0 V Conversion Time (1) Analog Input Voltage Analog Input Impedance ADC Reference Voltage ADC Reference Ground Analog input current ADC block current (2) tCON VIAN RAN AVREF AVSS IADIN IADC Min - Typ - Max 2 Unit LSB fOSC = 8 MHz - - - - AVREF = VDD = 5 V AVREF = VDD = 5 V AVREF = VDD = 5 V Power down mode 25 AVSS 2 2.5 VSS - - - - - - - - - 1 100 - AVREF - VDD VSS + 0.3 10 3 500 us V M V V uA mA nA NOTES: 1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion. 15-8 S3C880A/F880A MECHANICAL DATA 16 OVERVIEW #42 14.00 0.20 MECHANICAL DATA The S3C880A/F880A microcontrollers are available in 42-pin SIP package (42-SDIP-600), 44-pin QFP package (44QFP-1010B) . #22 0-15 #1 #21 0.20 39.50 MAX 39.10 0.20 0.50 (1.77) 1.00 0.10 0.10 1.78 NOTE: Dimensions are in millimeters. Figure 16-1. 42-Pin SDIP Package Dimensions (42-SDIP-600) 3.30 0.30 0.51 MIN 5.08 MAX 3.50 0.2 5 16-1 +0 . - 0 10 .05 42-SDIP-600 15.24 MECHANICAL DATA S3C880A/F880A 13.20 0.3 0-8 10.00 0.2 + 0.10 0.15 - 0.05 13.20 0.3 10.00 0.2 44-QFP-1010B 0.80 0.20 #1 0.80 + 0.10 0.10 MAX #44 0.35 - 0.05 (1.00) 0.05 MIN 2.05 0.10 2.30 MAX NOTE : Dimensions are in millimeters. Figure 16-2. 44-Pin QFP Package Dimensions (44-QFP-1010B) 16-2 S3C880A/F880A S3C880A/F880A MTP 17 OVERVIEW S3F880A MTP The S3C880A/F880A single-chip CMOS microcontroller is the MTP flash ROM version. It has an on-chip flash ROM instead of a masked ROM. The flash ROM is accessed by serial data format. PWM0/P2.5 PWM1/P2.1 PWM2/P2.2 (SCLK) PWM3/P2.3 (SDAT) PWM4/P2.4 PWM5/P2.0 T0/P2.6 T0CK/P1.7 ADC0/P3.0 ADC1/P3.1 ADC2/P0.6 ADC3/P0.7 TEST/TEST INT0/P1.0 INT1/P1.1 INT2/P1.2 INT3/P1.3 P1.4 P1.5 P1.6 OSDHT/P2.7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S3F880A (42-SDIP) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P0.0 P0.1 P0.2 P0.3 P0.4 VSS/VSS CAP.A P0.5 VDD/VDD nRESET/nRESET XOUT XIN VSS1 OSCOUT OSCIN V-sync H-sync Vblank Vred Vgreen Vblue Figure 17-1. S3F880A Pin Assignment (42-SDIP) 17-1 S3C880A/F880A MTP S3C880A/F880A P2.0/PWM5 P2.6/T0 P1.7/T0CLK P3.0/ADC0 P3.1/ADC1 P0.6/ADC2 P0.7/ADC3 TEST /TEST P1.0/INT0 P1.1/INT1 P1.2/INT2 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 P2.4/PWM4 P2.3/PWM3 P2.2/PWM2 (SCLK) P2.1/PWM1 (SDAT) P2.5/PWM0 P0.0 P0.1 P0.2 P0.3 P0.4 VSS S3F880A (44-QFP) 33 32 31 30 29 28 27 26 25 24 23 NC CAP.A P0.5 VDD/VDD nRESET/nRESET XOUT XIN VSS1 NC OSCOUT OSCIN Figure 17-2. S3F880A Pin Assignment (44-QFP) 17-2 P1.3/INT3 P1.4 P1.5 P1.6 P2.7/OSDHT Vblue Vgreen Vred Vblank H-sync V-sync 12 13 14 15 16 17 18 19 20 21 22 S3C880A/F880A S3C880A/F880A MTP Table 17-1. Descriptions of Pins Used to Read/Write the Flash ROM (S3F880A) Main Chip Pin Name P2.3 (Pin 4) P2.2 (Pin 3) TEST Pin Name SDAT SCLK VPP (TEST) Pin No. 4 (43) 3 (42) 13 (8) I/O I/O I/O I During Programming Function Serial data pin (output when reading, Input when writing) Input and push-pull output port can be assigned Serial clock pin (Input only pin) 0 V: operating mode 5 V: test mode 12.5 V: flash ROM writing mode 5 V: operating mode, 0 V: flash ROM writing mode Logic power supply pin. RESET VDD/VSS NOTE: RESET VDD/VSS 33 (29) 34/30, 37 (30/26, 34) I I Parentheses indicate pin number for 44-QFP package. 17-3 S3C880A/F880A MTP S3C880A/F880A NOTES 17-4 S3C880A/F880A DEVELOPMENT TOOLS 18 OVERVIEW SHINE DEVELOPMENT TOOLS Samsung provides a powerful and easy-to-use development support system in turnkey form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for S3C7, S3C8, S3C9 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options. Samsung Host Interface for in-circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted, added, or removed completely. SAMA ASSEMBLER The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary definition (DEF) file with device specific information. SASM88 The SASM88 is an relocatable assembler for Samsung's S3C8-series microcontrollers. The SASM88 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. The SASM88 supports macros and conditional assembly. It runs on the MS-DOS operating system. It produces the relocatable object code only, so the user should link object file. Object files can be linked with other object files and loaded into memory. HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code.(OBJ file) by HEX2ROM, the value 'FF' is filled into the unused ROM area up to the maximum ROM size of the target device automatically. 18-1 DEVELOPMENT TOOLS S3C880A/F880A TARGET BOARDS Target boards are available for all S3C8-series microcontrollers. All required target system cables and adapters are included with the device-specific target board. IBM-PC AT or Compatible RS-232C SMDS2+ PROM/OTP Writer Unit Target Application System RAM Break/Display Unit Probe Adapter Bus Trace/Timer Unit SAM8 Base Unit POD TB880A Target Board Eva Chip Power Supply Unit Figure 18-1. SMDS Product Configuration (SMDS2+) 18-2 S3C880A/F880A DEVELOPMENT TOOLS TB880A TARGET BOARD The TB880A target board is used for the S3C880A/F880A microcontrollers. It is supported with the SMDS2+. The TB880A target board can also be used for S3C880A/F880A. TB880A To User_VCC Off RESET 74HC4050 On 74HC10 Idle Stop VCC MDS 74HC4050 EPROM 27C512 GND J101 1 1 40-Pin Connector 21 External Triggers Ch1 Ch2 SMDS2 SMDS2+ SM1342A 22 CN 144 QFP S3E8800 EVA Chip L-C clock 42 + + 25 100-Pin Connector 1 Figure 18-2. TB880A Target Board Configuration 18-3 DEVELOPMENT TOOLS S3C880A/F880A Table 17-1. Power Selection Settings for TB880A 'To User_Vcc' Settings To User_VCC Off On TB880A VCC VSS VCC SMDS2+ Target System Operating Mode Comments The SMDS2+ main board supplies VCC to the target board (evaluation chip) and the target system. To User_VCC Off On TB880A External VCC VSS VCC SMDS2+ NOTE: Target System The SMDS2+ main board supplies VCC only to the target board (evaluation chip). The target system must have its own power supply. The following symbol in the 'To User_Vcc' Setting column indicates the electrical short (off) configuration: 18-4 S3C880A/F880A DEVELOPMENT TOOLS SMDS2+ Selection (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available. Table 17-2. The SMDS2 + Tool Selection Setting 'SW1' Setting SMDS2 SMDS2+ Operating Mode R/W SMDS2+ R/W Target System OSD Font ROM Selection Table 17-3. OSD Font ROM Selection Setting 'SW2' Setting MDS EPROM Comments EPROM (27C512) is used for OSD font ROM Not used MDS EPROM 18-5 DEVELOPMENT TOOLS S3C880A/F880A Table 17-4. Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part External Triggers Ch1 Ch2 Comments Connector from External Trigger Sources of the Application System You can connect an external trigger source to one of the two external trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace functions. 18-6 S3C880A/F880A DEVELOPMENT TOOLS J101 PWM0/P2.5 PWM1/P2.1 PWM2/P2.2 (SCLK) PWM3/P2.3 (SDAT) PWM4/P2.4 PWM5/P2.0 T0/P2.6 T0CK/P1.7 ADC0/P3.0 ADC1/P3.1 ADC2/P0.6 ADC3/P0.7 VSS INT0/P1.0 INT1/P1.1 INT2/P1.2 INT3/P1.3 P1.4 P1.5 P1.6 OSDHT/P2.7 NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P0.0 P0.1 P0.2 P0.3 P0.4 VSS CAP.A P0.5 VDD/VDD nRESET/nRESET N.C N.C VSS OSCOUT OSCIN V-sync H-sync Vblank Vred Vgreen Vblue NC NC NC NC Figure 17-3. 50-Pin DIP Connector J101 for TB880A 50-Pin DIP Connector Target Board J101 50-Pin DIP Connector 1 50 Part Name: AP42SD Order Cods: SM6538 1 Target System 42 1 50 S3C880A 42-SDIP Conversion PCB 25 26 21 25 26 22 Figure 17-4. S3C880A/F880A Probe Adapter for 42-SDIP Package 18-7 DEVELOPMENT TOOLS S3C880A/F880A NOTES 18-8 |
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